Catalytic effect of nano-thick gold electrodes on p-doping of diselenides during annealing process

Because of the weak interlayer van der Waals force, 2D materials are easily exfoliated from their bulk counterparts into one or a few atomic layers,^1–4 and this makes them promising materials for being stacked together to form various heterostructures with multiple functions. As a subgroup of 2D materials, transition metal dichalcogenides (TMDs) have many excellent physical properties, such as layered banding structures and strong interactions with light.^5–12 However, most TMDs have n-type dominant polarity, and this severely limits their potential for being designed into heterostructures for electronic and optoelectronic applications.^13–19 Therefore, much work has been done to establish easy and reliable ways to tune the polarity of TMDs,^20–23 among which thermal annealing has recently been studied extensively for modifying the electron density of TMDs.

Thermal annealing is used widely in semiconductor fabrication: it improves the performances of semiconductor devices by eliminating organic residues, reducing material defects, and enhancing the contact quality between the material and electrodes in high-temperature environments.^24–27 Also, it has been reported that thermal annealing modifies the polarity of TMDs,^28–30 but the mechanism of p-type doping of thermally annealed TMDs remains unclear, which reduces the reliability and reproducibility of the technique.

Herein, we systematically analyze the p-doping mechanism of thermal annealing to help establish a reliable doping method for TMDs. To study the mechanism, we use the example of 2D SnSe₂, which has a fairly high electron density of ∼10¹⁸ cm⁻³, leading to poor device performance.³¹ We report several sets of thermal annealing treatments performed on an SnSe₂ FET while controlling one of the annealing parameters for each set, and these results show that the oxidizing gas and nano-thick gold electrodes are two key parts for initiating the p-doping effects. The results of XPS and Auger electron spectroscopy (AES) verify the catalytic effect of nano-thick gold electrodes to oxidize and reduce the surface and electron density of SnSe₂, respectively, and after annealing in a suitable environment, the performance of the SnSe₂ FET improves greatly in terms of an on–off current ratio of up to ∼10³. This p-doping method is also shown to be valid for other TMDs including WSe₂ and MoSe₂.

Flakes of SnSe₂, WSe₂, and MoSe₂ were obtained from high-quality bulk crystals by mechanical exfoliation and then transferred immediately onto a p⁺-doped 285-nm Si/SiO₂ substrate. The bulk crystals used for mechanical exfoliation were purchased from Nanjing MKNANO Tech. Co., Ltd. After transfer, flakes were selected using optical microscopy and their exact thickness was measured using AFM. The electrodes were formed by EBL on a substrate covered with positron beam resist, and the metal electrodes were then deposited on the flakes. The experiments involved three electrodes made of different materials, i.e., chromium (Cr), gold (Au), and titanium (Ti). The metal electrodes were obtained using a thermic evaporator, and after deposition they were annealed in situ at 300 °C under high vacuum (10⁻⁵ Pa) for improved contact. Finally, a standard lifting process was used to finalize the fabrication. All these processes were carried out in ambient conditions with a constant humidity of 30% and a temperature of 23 °C.

Optical pictures were obtained using an optical microscope (XTZ-2030JX), and AFM pictures were obtained using a Bruker Dimension Icon. The annealing of the SnSe₂ FET was carried out using a rapid annealing furnace (LABSYS RTP-1200) in different gas environments. Raman spectra were obtained using a Renishaw InVia Raman spectrometer with an excitation wavelength of 532 nm. The electronic properties were measured in ambient air by a semiconductor analyzer (Agilent B1500A). AES was performed using a PHI 710 at an accelerating voltage of 5 kV and an electron beam current of 10 nA.

The structure of the layered SnSe₂ crystal is shown schematically in Fig. 1(a), showing hexagonal symmetry and a sandwich-like structure. SnSe₂ flakes with a few layers were obtained from high-quality bulk crystals by mechanical exfoliation, transferred onto a Si wafer covered with 285-nm SiO₂, and then measured for thickness using AFM. The SnSe₂ FET was fabricated using standard photolithography, with Cr/Au (10/30 nm) contacts deposited, and its electrical measurement is shown schematically in Fig. 1(b).

Figures 1(c) and 1(d) show respectively the transfer [in both linear and semilogarithmic (inset) scales] and output curves of the SnSe₂ FET before and after annealing. In Fig. 1(c), the red line represents the transfer curve of the pristine SnSe₂ FET when the source–drain bias (V_ds) was held at 100 mV, and the on–off ratio is the ratio of current in the on and off states of the device. The input voltage corresponding to the midpoint of the transition zone in the transfer characteristic curve where the output current changes sharply with a change in the input voltage is called the threshold voltage (V_th). How V_th changes offers a clear indication of n- or p-doping, and a positive shift in V_th for an n-type transistor indicates that p-doping is occurring. Upon sweeping the back-gate V_g from −60 to 60 V, the few-layer SnSe₂ exhibits stubborn n-type conduction with an electron mobility of about 21 cm⁻²⋅V⁻¹⋅s⁻¹ as obtained from μ = [L/(WC_iV_ds)] × [dI_ds/dV_g],³² where L and W are the channel length and width, respectively, and C_i is the capacitance per unit area of the back-gate insulator. We derive V_th by extrapolating the linear part of the transfer curve according to I_ds = (WC_iV_ds/L) × (V_g − V_th), resulting in V_th ≈ −201 V for the device. This suggests that the gate voltage could not modulate the drain current to turn off the SnSe₂ FET effectively. This was because the gate potential was shielded by the ultra-high carrier density of the pristine SnSe₂, as reported previously.^26,31 For improved electrical performance, the SnSe₂ FET was subjected to rapid thermal annealing at 300 °C using air (78% nitrogen, 21% oxygen, and 1% other gases) as the annealing atmosphere. After annealing, the device performance was significantly improved. The blue transfer curve represents the characteristics of the device after 10 min of rapid annealing. After annealing, I_ds at −60 V drops continuously from 667 nA before annealing to about 25 pA, which increases the on–off ratio of the degenerately n-doped semiconducting SnSe₂ from 1 to 4 × 10³. The output characteristics of the device shown in Fig. 1(d) indicate that the metal contacts connect well.

Figure 2 characterizes the pristine SnSe₂ flakes without deposition of Cr/Au contacts before and after annealing in air in order to establish the reason for the optimized device performance. First, Raman spectroscopy was used to explore how annealing affects the main SnSe₂ phonon modes; the Raman spectra have two important modes, i.e., the E_g (in plane) and A_1g (out of plane) modes located at 117.2 and 186.3 cm⁻¹, respectively, consistent with previous reports.³²  Figure 2(a) shows the Raman spectrum of the same SnSe₂ flake before (black) and after (red) annealing, with the slight blue shift in the E_g phonon mode suggesting p-doping of the degenerately semiconducting SnSe₂.³³ Furthermore, AFM was used to measure the flake thickness before and after annealing. To assess whether the etching effect has an impact on optimizing the device performance, a control experiment was carried out. Figure 2(b) shows optical microscopy images of pristine SnSe₂ annealed in air at 300 °C for 10 min, and as can be seen, the flake color approached the substrate color after annealing, which indicates a thinner flake. Next, two Cr/Au electrodes were deposited on the annealed SnSe₂ flake, after which an optical image and the transfer characteristic curves of the device were obtained. When the gate voltage was increased from −60 to 60 V, I_ds increased from 204 nA to only 240 nA; the device performance did not improve significantly, which means that annealing the material without gold electrodes does not result in a favorable switching ratio. Instead, the gold electrodes may play a dominant role.

As shown in Figs. 2(c) and 2(d), the flake thickness changed from 22.8 to 13.5 nm, showing that thermal annealing in oxygen has an etching effect. However, the SnSe₂ flake did not continue to thin after 10 min of annealing, indicating a threshold for the etching effect. Figures 2(e)–2(h) were obtained under the same annealing conditions using SnSe₂ films with an initial thickness of 37.3 and 54.7 nm, respectively, to find the threshold value. As can be seen, the SnSe₂ flakes of different thicknesses were thinned by 9–12 nm after annealing.

Figure 3 shows the role of the Au contacts in improving device performance. First, different metals were used as contacts to measure the performance of the SnSe₂ FET. Figure 3(a) shows the transfer curves of the SnSe₂ FET using Ti (orange) and Cr (purple) before (solid) and after (dotted) annealing, with a fixed contact thickness of 30 nm. As can be seen, the device using either Ti or Cr electrodes showed reduced I_ds rather than enhanced on–off ratio, showing the necessity of using Au in the annealing process to improve the performance of the SnSe₂ device. This can be explained by the catalytic effect of the nano-thick Au contacts.^34–40 Because the nano-thick gold electrodes form gold clusters during the annealing process, the nano-gold clusters can activate O₂. Many studies have shown that because the gold clusters form a core–shell structure (i.e., a positively charged nucleus and a negatively charged shell), the negatively charged active sites are susceptible to O₂ activation. During the O₂ activation process, the electron concentration on the surface of SnSe₂ decreases because of the oxidation taking away more electrons, which improves the gate modulation effect.

Next, we investigate the catalytically affected area. One pair of electrodes (Cr/Au = 10 nm/30 nm) was deposited on the SnSe₂ material, labeled as electrode 1 in the inset of Fig. 3(b), which shows the transfer curves before (red) and after (green) annealing. Before annealing, the SnSe₂ device could not be turned off, but after annealing the device performance was improved by three orders of magnitude in terms of switching ratio. Then, another pair of electrodes (Cr/Au = 10 nm/30 nm) was deposition on the annealed material, labeled as electrode 2 in the inset of Fig. 3(b) (blue line). The second pair of electrodes was designed to be a certain distance from the first pair. The transfer curve obtained with electrode 2 exhibits improved performance similar to that obtained with electrode 1. This shows that the catalytic effect of the gold electrodes was not confined to the immediate vicinity of the electrodes but rather was spread over the entire surface of the device. To investigate how the electrode deposition process affects the device performance, the transfer curve with the first pair of electrodes was obtained again after the second pair had been deposited (orange line), which showed no significant change.

Figure 4 analyzes the composition of the SnSe₂ surface annealed with and without gold electrodes via XPS and AES. Figures 4(a)–4(c) show the XPS spectra of Sn, Se, and O, respectively, after annealing with (orange) and without (purple) gold electrodes. For the case of annealing without gold electrodes, the Sn spectrum has two peaks at 487.31 and 495.72 eV, the Se spectrum has one peak at 54.79 eV, and the O spectrum has a characteristic peak at 531.9 eV, which all agree with the positions reported previously.^41,42 Compared to the case of annealing with gold electrodes, no obvious differences are observed in both the Sn and O spectra. In contrast, the Se spectrum has a new peak at 59.30 eV after annealing with gold electrodes, which corresponds to the Se⁴⁺ peak, while that at 54.79 eV corresponds to Se²⁻.^43,44 This shows that the catalytically reacted O₂ has stronger oxidation activity to convert Se²⁻ to Se⁴⁺. Previous studies have shown that SnSe₂ oxidation increases the work function of the surface.^45,46 Figures 4(d) and 4(e) show the results of the AES analysis of the samples; the percentage elemental content of the samples without annealed electrode deposition is Se: O: Sn = 65.3%: 5.5%: 5.5%, whereas with annealed gold electrodes it is 22.2%: 58.6%: 19.2%. Compared to the samples annealed without gold electrodes, there is an increase in O content and a decrease in Se content in the samples annealed with gold electrodes, which once again proves the generation of SeO₂.

Figure 5 shows the effect of annealing on the electrical characteristics of MoSe₂ and WSe₂ FET devices in an air environment. The Raman spectra of MoSe₂ and WSe₂ before and after annealing are shown in Figs. 5(b) and 5(c), respectively. Analogous to SnSe₂, the annealed diselenides are blue shifted (to higher energy) on account of p-doping. Figure 5(c) shows the transfer curves of the MoSe₂ FET (orange) with gold electrodes after annealing and compares them with those of the pristine MoSe₂ FET (green). The pristine MoSe₂ FET exhibited n-type dominant bipolarity and became p-type after annealing for 10 min in a rapid annealing furnace; the equivalent experiment for WSe₂ is reported in Fig. 5(d), where the transfer characteristic curve for pristine WSe₂ shows a pronounced bipolarity, and the annealed treatment shows significant p-doping. Figure 5(e) compares the threshold voltage between the annealed diselenides FET and the pristine sample; the theoretically low turn-off voltage of SnSe₂ is not shown. Several transistors were measured in each case to obtain the average and the standard deviation indicated by the error bars. The annealing treatment of the gold electrodes is verified by the occurrence of variable degrees of p-doping in the samples. In the literature, degenerately n-doped semiconducting SnSe₂ devices are mostly reported to show stubborn n-type behavior, even with high-work-function metal contacts (e.g., Au) because of Fermi-level pinning at the interface,⁴⁷ whereas WSe₂ and MoSe₂ are located in the middle of the bandgap, pin-pinning does not occur, and thus polarity modulation is relatively easy.³³ 

In summary, this work has revealed the mechanism whereby thermal annealing leads to the p-doping of 2D TMDs. It is caused mainly by the oxidation of dichalcogenide atoms in an oxygen-containing environment under high temperature, and the catalytic effect of nano-thick gold electrodes also plays an important role in initiating the oxidation process. Using this means, the SnSe₂ FET could be turned off to achieve an on–off ratio of 4 × 10³, while the WSe₂ and MoSe₂ FETs were tuned from n-type to p-type dominant polarity. These findings provide a solid foundation for establishing a reliable doping technique for 2D TMDs.

See the supplementary material for Fig. S1.

This work was supported by the National Natural Science Foundation of China (Grant Nos. 52075385 and 12034001), the National Key R&D Program (Grant No. 2018YFA0307200), and the 111 Project (Grant No. B07014).

The authors have no conflicts to disclose.

The data that support the findings of this study are available within the article.

Yan Wang received a bachelor’s degree from Shandong University in 2019 and is now working for a Ph.D. degree at Tianjin University. Her research interests include performance modulation of 2D materials and devices, emerging nonvolatile memory, and neuromorphic computing.

Jing Liu is currently a professor in the School of Precision Instrumentation and Optoelectronic Engineering at Tianjin University. She received B.S. and M.S. degrees from Huazhong University of Science and Technology and a Ph.D. degree from the University of Michigan. Her research interests include nanomaterial functional devices, sensor device applications, and flexible wearable devices.