Although a high-quality homoepitaxial layer of 4H-silicon carbide (4H-SiC) can be obtained on a 4° off-axis substrate using chemical vapor deposition, the reduction of defects is still a focus of research. In this study, several kinds of surface defects in the 4H-SiC homoepitaxial layer are systemically investigated, including triangles, carrots, surface pits, basal plane dislocations, and step bunching. The morphologies and structures of surface defects are further discussed via optical microscopy and potassium hydroxide-based defect selective etching analysis. Through research and analysis, we found that the origin of surface defects in the 4H-SiC homoepitaxial layer can be attributed to two aspects: the propagation of substrate defects, such as scratches, dislocation, and inclusion, and improper process parameters during epitaxial growth, such as in-situ etch, C/Si ratio, and growth temperature. It is believed that the surface defects in the 4H-SiC homoepitaxial layer can be significantly decreased by precisely controlling the chemistry on the deposition surface during the growth process.

  • The growth process of the 4H-SiC homoepitaxial layer is introduced.

  • Surface defects in the 4H-SiC homoepitaxial layer are discussed, including the origin, mechanism, and characterization.

  • The controlling methods of surface defects in the 4H-SiC growth process are detailed.

Owing to the recent progress in the growth and device technologies of wide-bandgap semiconductors, these materials are now considered realistic candidates for advanced power devices that outperform Si-based devices. Among these materials, silicon carbide (SiC), due to its wide bandgap, high electric breakdown field, high thermal conductivity, and high carrier saturation velocity, is a potential semiconductor material that can be extensively applied in different fields with high power, high voltage, high temperature, and high frequency.1 In addition, SiC has the following advantages: p- and n-type doping control in a wide range by either in-situ doping during growth or ion implantation, availability of a native oxide, and relatively long carrier lifetimes for bipolar devices due to its indirect band structure.2,3

Since the first production of SiC Schottky barrier diodes in 2001 and SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) in 2010, the market of SiC unipolar power devices (mainly 1 kV class) has gradually been growing, demonstrating remarkable energy efficiency in real electronic systems.4,5 Currently, the commercialized 650–1700 V SiC Schottky barrier diodes have been widely applied in many fields, such as consumer electronics with power adaptors and battery chargers.6,7 SiC MOSFETs have been used in a few systems in the industrial filed, but they are still at the beginning stage of development. Moreover, high-voltage and high-current devices are still being developed because of the inhibitions of factors, such as high cost, poor quality of epitaxial wafers, and low process technology. In recent years, we have witnessed a growing market of high-voltage particle accelerators for medical applications, where the voltage of power supply reaches 3.3–30 kV. Generally, the device structures are realized by epitaxial growth on 4H-SiC substrates, so high-quality epitaxial wafers are essential for the development of high-performance power electronic devices.8 In the past 10 years, the growth process of the 4H-SiC homoepitaxial layer has been significantly improved. The introduction of chloride precursors, epitaxial growth on large-area substrates with low defect densities, improvement of the surface morphology, the understanding of the chemical vapor deposition (CVD) reactions, and epitaxial mechanisms by advanced simulations are just the main recent research areas and development progress obtained in the 4H-SiC homoepitaxial process.9–11 Aside from these, the high cost of 4H-SiC is an important problem, and its price is 4–6 times that of silicon devices. Indeed, for a 1.2 kV Schottky diode, the cost of this process reaches 25%–30% of the total device cost. Therefore, the cost reduction of 4H-SiC homoepitaxial layer is a future research focus.

In this work, several common surface defects in the 4H-SiC homoepitaxial layer are reported. These surface defects are discussed, including the origin, morphology feature, characterization, and reduction method. The findings show that a low surface defect density of the 4H-SiC epitaxial layer can be obtained by carefully controlling the surface chemistry of the CVD process.

4H-SiC homoepitaxial wafers were grown on 6-in. 4° off-axis Si-face 4H-SiC substrates through the CVD method.12 Commercial-production-grade 6-in. 4H-SiC substrates were used. The structure of the epitaxial wafer is shown in Fig. 1. Silane (SiH4), trichlorosilane (TCS), ethylene (C2H4), and propane (C3H8) are usually used as silicon precursors and carbon precursors during growth process. The carrier gas was hydrogen (H2), and the n-type doping gas was nitrogen (N2).13 The growth temperature and pressure are 1500–1650 °C and 50–150 mbar, respectively. Fig. 2 shows the process sequence used for the 4H-SiC homoepitaxial growth process. The growth process of 4H-SiC homoepitaxial wafers considers the ramp temperature, in-situ etch, epitaxial growth, and cool-down, as shown in Fig. 2. In-situ etching was primarily performed before the drift layer growth using pure H2, HCl/H2, hydrocarbon/H2, or SiH4/H2 at high temperatures of 1500–1650 °C.13,14 The purpose of in-situ etching is to remove the subsurface damage due to substrate polishing and to obtain regular step structures. The proper process parameter of the drift layer growth is extremely important to obtain high-quality epitaxial wafers. These parameters include the growth temperature, pressure, C/Si ratio, and Cl/Si ratio. The C/Si ratio is an extremely important parameter, and the good surface morphology is obtained under a fixed range. When the C/Si ratio is too low, the surface suffers from the formation of severe macrosteps and Si droplets. By contrast, surface morphological defects, such as triangle defects, are easily generated when the C/Si ratio is too high.2,15

Fig. 1.

Structure chart of the 4H-SiC homoepitaxial wafer.

Fig. 1.

Structure chart of the 4H-SiC homoepitaxial wafer.

Close modal
Fig. 2.

Process sequence of the 4H-SiC homoepitaxial layer using CVD.

Fig. 2.

Process sequence of the 4H-SiC homoepitaxial layer using CVD.

Close modal

The drift layer, as an important part of power electronic devices, directly influences the performance of devices. Thus, it is very important that a high-quality drift layer can be obtained for the development of high-performance power electronic devices. Currently, the quality of the epitaxial layer is evaluated by two parameters: uniformity and defect density of the epitaxial layer. The distribution of the breakdown voltage of devices in wafer depends on the uniformity of the epitaxial wafer with thickness and doping concentration, and the typical values of uniformity for the thickness and doping concentration are not more than 1.5% and 6.0%, respectively. The thickness of the epitaxial layer was determined through a Fourier transform infrared spectrometer (Thermo Scientific, Nicolet iS50), and the doping concentration was obtained through a capacitance–voltage measurement using a Hg Schottky contact (Semilab Corp., MCV-530). The edge exclusion is 5 mm in the measurement process.

The defect in the epitaxial layer has a negative effect on the performance of SiC power electronic devices, such as low breakdown voltage, high leakage current, and poor stability. Morphological defect distribution was measured and counted using an inspection tool (LaserTec Co., SICA88) or the same precision-level inspection tool. Meanwhile, the surface defect density of the 4H-SiC epitaxial layer can be carefully controlled at approximately 1 cm−2. Although the quality of the current 4° off-axis 4H-SiC epitaxial layers has been obviously improved in recent years, they still cannot satisfy the requirements of high-voltage devices above 6.5 kV due to their extremely low yield. Thus, further defect reduction in epitaxial layers is still one of the research focuses. The common morphological defects in the epitaxial layer include triangles, carrots, pits, step bunching, stacking faults, dislocations, downfalls, and downfall triangles, and these defects have different influences on the performance of the device.16,17 The defect origin of the epitaxial layer can be divided into two aspects. First, the defect is generated during the epitaxial process, or the so-called process-induced defect. Second, some defects come from the substrate, or the so-called extended defects. In the paper, several morphological defects are discussed to decrease the defect density in the 4H-SiC epitaxial layer.

The triangle defect is one of the most common surface defects in the 4° off-cut 4H-SiC epitaxial layer. This kind of defect gives rise to negative and serious impacts on the yield ratio and reliability of a device, or the so-called killer defects.18 Hence, systematic investigations on the origins and morphologies of the triangle defects are necessary. The morphology of triangle defects can be clearly seen using an optical microscope with high magnification. Fig. 3(a) and (b) show the different morphologies of triangle defects using an optical microscope. The formation mechanism of triangle defects in the 4H-SiC epitaxial layer is presented in Fig. 3(c). The formation of triangle defects is believed to be ascribed to the two-dimensional (2D) nucleation on terraces, which affects the growth of the step flow.19,20 Through a morphological observation of Fig. 3(a) and (b), it is found that triangle defects can be divided into two types: obtuse triangle and acute triangle. Many reports have attributed the origin of obtuse triangle defects to surface scratches, foreign materials, and micropipes. These defects can be effectively reduced by improving the substrate surface and operation environment. Another type of acute triangle defects is ascribed to the improper parameters of the growth process, and shallow profiles can be observed using optical microscopy. In recent years, several ways have been studied to further reduce acute triangle defects. The triangle defects in the 4H-SiC epitaxial layer can be effectively controlled through the adjustment of the growth process parameters of the temperature and C/Si ratio. Generally, the triangle defect density of the 4H-SiC epitaxial layer can be reduced to 0.39 cm−2 with increasing growth temperature, as shown in Fig. 4. The reasons for the reduction of the triangle defect density are as follows: First, the migration rate of an adatom on the deposition surface is increased, which effectively inhibited the 2D nucleation on the terraces. Second, the effective C/Si ratio on the deposition surface is reduced under a higher temperature, which enhances the step flow growth during the epitaxial growth. Therefore, the low triangle defect density of the 4H-SiC epitaxial layer can be obtained through the optimization of the substrate surface and growth process.

Fig. 3.

General types (a-b) and formation mechanism (c) of the triangle defect in epitaxial layers.

Fig. 3.

General types (a-b) and formation mechanism (c) of the triangle defect in epitaxial layers.

Close modal
Fig. 4.

Triangle defect density of epitaxial wafers at different growth temperatures.

Fig. 4.

Triangle defect density of epitaxial wafers at different growth temperatures.

Close modal

The carrot defect is one of the major surface morphological defects that appear in as-grown epitaxial layers, and it was reported to increase the reverse leakage current of 4H-SiC Schottky and p–n junction diodes.21,22 The different structures and origins of the carrot defect have been proposed in many papers.21,23 The carrot defect is extended along the step-flow direction in the epitaxial layers. Fig. 5(a) shows the morphology of the carrot defect in the 4H-SiC epitaxial layer. It can be seen that the carrot defect consists of ridges. To further analyze the formation of carrot defects, the 4H-SiC epitaxial layer was etched using molten KOH at 500 °C for 30 min. The microscopic images of the carrot defect after molten KOH corrosion is shown in Fig. 5(b). By using the molten KOH etching method, it is found that the carrot defect consists of a threading screw dislocation (TSD)-related etch pit as the starting point and a pair of basal plane dislocation (BPD)-related etch pits as the terminating point, and the starting and terminating points are connected by a typical stacking fault intersecting the epitaxial layer surface. Meanwhile, the different origins of the carrot defect have been presented in previous reports, such as dislocations with TSDs and BPDs, dislocation slip bands, and substrate surface scratches.24,25 Based on these reasons, their densities can be effectively reduced using the following methods. First, the significant decrease in the density of carrot defects was observed using the in-situ etching prior to the epitaxial growth.24 The reduction of the carrot defect density is ascribed to the morphological improvement of the substrate surface. In addition, the formation of the carrot defect density can be avoided under Si-rich conditions due to the resulting improvement in the growth of the step flow.

Fig. 5.

Microscopic images of the carrot defect: (a) morphology on the epitaxial surface; (b) etched by molten KOH.

Fig. 5.

Microscopic images of the carrot defect: (a) morphology on the epitaxial surface; (b) etched by molten KOH.

Close modal

With the development of industrial technology, surface pits have become a new issue due to their very high density. The surface pits of the epitaxial layer can cause the occurrence of a local electric field crowding, resulting in negative effects on the device performance.26,27 In many previous reports, the morphology and origin of surface pits have been studied in depth using the selective etching method and synchrotron reflection X-ray topography. The microscopic images of the surface pits are shown in Fig. 6. Currently, it was demonstrated that the surface pits can be originated from the threading screw dislocations and threading edge dislocation (TED) sites during the epitaxial growth of 4H-SiC.28,29 The observed dislocation-induced surface pits according to their shape are classified into two types. One is deep pits, whose typical lateral size is a few μm with a depth of a few tens of nm, and the other is shallow pits, whose typical lateral size and depth are approximately 1 μm and a few nm, respectively.30 The difference of the pit shape originates from the improvement of the kinetics of the step-flow growth and the controllability of the ingredients supplied to the substrate surface. By analyzing the shape of the surface pits, the deep pits had an effect on the leakage current of the Schottky barrier diodes and lifetime of the metal–oxide–semiconductor capacitor. The influence of the process parameters on the formation and reduction of surface pits on the 4H-SiC epitaxial layer has been investigated, such as C/Si ratio, pre-etching prior to the growth process, growth temperature, and growth rate.31,32 Chen et al. revealed that a lower surface pit density can be prepared using a lower C/Si ratio even though a substrate may have a high dislocation density. Generally, the different shapes of surface pits depend on the C/Si ratio for the epitaxial growth, and the shape of surface pits gradually becomes a deep pit under a high-C/Si-ratio condition. The surface pits of epitaxial layers can be reduced using the following factors: First, the origination of surface pits can be reduced by the quality improvement of the substrate, such as low TSDs and TEDs. Second, the optimized growth conditions can effectively eliminate defects generated during the epitaxial growth, such as lower C/Si ratio and growth rate.

Fig. 6.

Morphology of surface pits using the optical microscope.

Fig. 6.

Morphology of surface pits using the optical microscope.

Close modal

Step bunching is another kind of morphology defect. The step bunching defect occurs on the surface of the 4H-SiC epitaxial layer, and its profile can be observed using an optical microscope. Step bunching can induce a crucial problem in high-power devices where the rough junction interface causes electric field crowding, resulting in the reduction of blocking voltages. In addition, it has an important effect on the channel mobility or the oxide breakdown characteristics in MOSFETs.33 The morphology of step bunching is perpendicular to the primary orientation flat shown in Fig. 7. Although various explanations of the formation of step bunching have been provided, the formation mechanism has not been aptly explained until now. At present, the free step bunching of the 4H-SiC epitaxial layer is achieved by the improvement of process parameters, namely, in-situ etch, growth temperature, and C/Si ratio.34Fig. 7 presents the effect of growth temperature on step bunching in the growth process. The formation of step bunching is attributed to the different growth rates with [1−100] and [11−20] orientations.35 The growth rate with [1–100] and [11–20] orientations is gradually the same when the growth temperature is decreasing. Therefore, the formation of step bunching on the 4H-SiC epitaxial layer can be avoided by carefully controlling the chemistry temperature on the deposition surface during the growth process.

Fig. 7.

Step bunching of the surface for 4H-SiC epitaxial wafers at different growth temperatures.

Fig. 7.

Step bunching of the surface for 4H-SiC epitaxial wafers at different growth temperatures.

Close modal

Generally, there are three different dislocations in commercial 4H-SiC substrates: TSDs with a typical density of 300–500 cm−2, BPDs with a typical density of 500–1000 cm−2, and TEDs with a typical density of 2000–5000 cm−2. These dislocations in the substrate can propagate into the epitaxial layer during the epitaxial growth due to the growth mode of the step flow.36 Almost all TSDs and TEDs in the substrate are replicated in the epitaxial layer, and it is hard to eliminate them using the epitaxial method. However, most (>90%) BPDs in the substrate are converted to TEDs within a few micrometers of an initial epitaxial layer without any special treatment, and the rest is propagated in a SiC epitaxial layer along the basal plane during epitaxial growth. The TSDs and TEDs have no evident influence on the performance of Schottky barrier diode devices, but the BPDs in the epitaxial layer are considered the source of stacking faults that lead to the performance degradation of bipolar devices with a forward voltage drift and reverse leakage current.36 Therefore, decreasing the density of BPDs in epitaxial layers is a key issue. A BPD in 4H-SiC can be dissociated into two partial dislocations with a stacking fault enclosing between them, as shown in Fig. 8(a).37 

Fig. 8.

Decomposition schematic (a) and conversion process (b) of BPDs.

Fig. 8.

Decomposition schematic (a) and conversion process (b) of BPDs.

Close modal

The step flow growth in the down-step direction and lateral growth perpendicular to the step flow direction can simultaneously take place during the epitaxial growth.37 The growth mode of the step flow is beneficial to the formation of the homoepitaxial layer, and it induces the propagation of the substrate crystalline structure to the epitaxial layer. The lateral growth mode is thought to form a 2D island nucleation, which leads to the increase in surface defects. In the step flow growth domination, the BPDs in the substrate propagate into the epitaxial layer. On the contrary, the two sides of BPD etch pits will come closer and merge, and the BPDs are converted to TEDs in the epitaxial growth. The conversion process of BPD to TED during epitaxial growth is depicted in Fig. 8(b). In Fig. 8(b), the shell shape of BPD is observed using the molten KOH. By the analysis of BPD to TED conversion, it is believed that the conversion effectiveness of BPDs to TEDs can be enhanced by optimization of process parameter, such as in-situ etching, buffer process, interruption growth, and C/Si ratio in the drift layer.38 The effect of the C/Si ratio and in-situ etching on conversion effectiveness of BPDs to TEDs during epitaxial growth was presented in our previous work.39 

In this work, several defects in the 4H-SiC homoepitaxial layer are discussed, including the origin, mechanism, characterization, and negative impact on devices. Meanwhile, the controlling methods of different defects are studied in detail. It is suggested that the defects in the 4H-SiC epitaxial layer can be reduced by the following aspects: through the improvement of the 4H-SiC substrate quality, such as reduction of the dislocation density, and through the optimization of process parameters, such as growth temperature. Therefore, the lowest defect density of the 4H-SiC homoepitaxial layer can be prepared by accurately controlling the surface chemistry during the growth process. In addition, the development of 4H-SiC epitaxial layer with large diameter and fast growth rate for the epitaxial process is a research focus in the future.

The authors declare no conflict of interest.

This work was supported by the Provincial Government of Shanxi [Grant No. 20201102012].

1.
La Via
F
,
Camarda
M
,
La Magna
A
.
Mechanisms of growth and defect properties of epitaxial SiC
.
Appl Phys Rev
2014
;
1
(
3
).
2.
Kimoto
T
.
Bulk and epitaxial growth of silicon carbide
.
Prog Cryst Growth Charact. Mater.
2016
;
62
:
329
351
.
3.
Kimoto
T
,
Cooper
JA
.
Fundamentals of Silicon Carbide Technology
.
Singapore
:
John Wiley & Sons
;
2014
. p.
75
124
.
6.
Kimoto
T
,
Yonezawa
Y
.
Current status and perspectives of ultrahigh-voltage SiC power devices
.
Mater Sci Semicond Process
2018
;
78
:
43
56
.
7.
Casady
JB
,
Johnson
RW
.
Status of silicon carbide (SiC) as a wide-bandgap semiconductor for high-temperature application: A review
.
Solid State Electron
1996
;
39
:
1409
1422
.
8.
Miyazawa
T
,
Nakayama
K
,
Tanaka
A
, et al 
Epitaxial growth and characterization of thick multi-layer 4H-SiC for very high-voltage insulated gate bipolar transistors
.
J Appl Phys
2015
;
118
:
085702
.
9.
La Via
F
,
Galvagno
G
,
Foti
G
, et al 
4H SiC epitaxial growth with chlorine addition
.
Chem Vap Depos
2006
;
12
:
509
515
.
10.
Okada
T
,
Okamoto
K
,
Ochi
K
, et al 
Origin of surface morphological defects in 4H-SiC Homoepitaxial films
.
Mater Sci Forum
2006
;
527-529
:
399
402
.
11.
Veneroni
A
,
Masi
M
.
Gas-phase and surface kinetics of epitaxial silicon carbide growth involving chlorine-containing species
.
Chem Vap Depos
2006
;
12
:
562
568
.
12.
Zhao
LX
,
Yang
L
,
Wu
HW
.
High quality 4H-SiC homo-epitaxial wafer using the optimal C/Si ratio
.
J Cryst Growth
2020
;
530
:
125302
.
13.
Sun
Y
,
Feng
G
,
Zhang
J
, et al 
Reduction of epitaxial defects on 4°- off 4H-SiC homoepitaxial growth by optimizing in-situ etching process
.
Superlattice Microst
2016
;
99
:
145
150
.
14.
Kojima
K
,
Kuroda
S
,
Okumura
H
, et al 
Effect of additional Silane on in-situ H2 etching prior to 4H-SiC homoepitaxial growth
.
Mater Sci Forum
2007
;
556-557
:
85
88
..
15.
Fujiwara
H
,
Danno
K
,
Kimoto
T
, et al 
Effects of C/Si ratio in fast epitaxial growth of 4H–SiC (0001) by vertical hot-wall chemical vapor deposition
.
J Cryst Growth
2005
;
81
:
370
376
.
16.
Yamashita
T
,
Momose
K
,
Muto
D
, et al 
Characterization of triangular-defects in 4°off 4H-SiC epitaxial wafers by synchrotron X-ray topography and by transmission electron microscopy
.
Mater Sci Forum
2012
;
717-720
:
363
366
.
17.
Tsuchida
H
,
Ito
M
,
Kamata
I
, et al 
Formation of extended defects in 4H-SiC epitaxial growth and development of a fast growth technique
.
Phys Status Solidi B
2009
;
246
(
7
):
1553
1568
.
18.
Das
H
,
Sunkari
S
,
Justice
J
,
et al.
Statistical analysis of killer and non-killer defects in SiC and the impacts to device performance
.
Mater Sci Forum
2019
;
1004
:
458
463
.
19.
Shrivastaca
A
,
Muzykov
P
,
Caldwell
JD
, et al 
Study of triangular defects and inverted pyramids in 4H-SiC 4°off-cut(0001) Si face epilayers
.
J Cryst Growth
2008
;
310
:
4443
4450
.
20.
Das
H
,
Melnychuk
G
,
Koshka
Y
.
Triangular defects in the low-temperature halo-carbon homoepitaxial growth of 4H-SiC
.
J Cryst Growth
2010
;
312
:
1912
1919
.
21.
Hassan
J
,
Henry
A
,
McNally
PJ
, et al 
Characterization of the carrot defect in 4H-SiC epitaxial layers
.
J Cryst Growth
2010
;
312
:
1828
1837
.
22.
Zhang
X
,
Ha
S
,
Benamara
M
, et al 
Cross-sectional structure of carrot defects in 4H–SiC epilayers
.
Appl Phys Lett
2004
;
85
:
5209
5211
.
23.
Tsuchida
H
,
Ito
M
,
Kamata
I
, et al 
Formation of extended defects in 4H-SiC epitaxial growth and development of a fast growth technique
.
Phys Status Solidi B
2009
;
7
:
1553
1568
.
24.
Yazdanfar
M
,
Leone
S
,
Pedersen
H
, et al 
Carrot defect control in chloride-based CVD through optimized ramp up conditions
.
Mater Sci Forum
2012
;
717-720
:
109
112
.
25.
Dong
L
,
Sun
G
,
Yu
J
, et al 
Structure and origin of carrot defects on 4H-SiC homoepitaxial layers
.
Mater Sci Forum
2014
;
778-780
:
354
357
.
26.
Kudou
C
,
Asamizu
H
,
Tamura
K
, et al 
Influence of epi-layer growth pits on SiC device characteristics
.
Mater Sci Forum
2015
;
821-823
:
177
180
.
27.
Ohtani
N
,
Ushio
S
,
Kaneko
T
, et al 
Tunneling atomic force microscopy studies on surface growth pits due to dislocations in 4H-SiC epitaxial layers
.
J Eelectron Mater
2012
;
41
:
2193
2196
.
28.
Ma
X
,
Chang
H
,
Zhang
Q
, et al 
Investigation on small growth pits in 4H silicon carbide epilayers
.
J Cryst Growth
2005
;
279
:
425
432
.
29.
Picard
YN
,
Liu
KX
,
Stahlbush
RE
, et al 
Imaging surface pits and dislocations in 4H-SiC by Forescattered Electron detection and photoluminescence
.
J Electron Mater
2008
;
37
:
655
661
.
30.
Sun
Y
,
Feng
G
,
Kang
J
, et al 
Formation and reduction of large growth pits on 100 mm 4° 4H-SiC
.
Mater Sci Forum
2015
;
858
:
193
196
.
31.
Anzalone
R
,
Piluso
N
,
Salanitri
M
, et al 
Hydrogen etching influence on 4H-SiC homo-epitaxial layer for high power device
.
Mater Sci Forum
2017
;
897
:
71
74
.
32.
Chen
W
,
Ho
H
,
Yang
P
, et al 
The relationship between surface pits density and growth parameters during the epitaxial growth of 4H-SiC
.
Mater Sci Forum
2016
;
858
:
229
232
.
33.
Kimoto
T
,
Itoh
A
,
Matsunami
H
, et al 
Step bunching mechanism in chemical vapor deposition of 6H– and 4H–SiC (0001)
.
J Appl Phys
1997
;
81
(
8
):
3494
3500
.
34.
Wada
K
,
Kimoto
T
,
Nishikaw
T
, et al 
Epitaxial growth of 4H–SiC on 4° off-axis (0001) and (000−1)substrates by hot-wall chemical vapor deposition
.
J Cryst Growth
2006
;
291
:
370
374
.
35.
Syvajarvi
M
,
Yakimova
R
,
Janzen
E
.
Step-bunching in SiC epitaxy: Anisotropy and influence of growth temperature
.
J Cryst Growth
2002
;
236
:
297
304
.
36.
Song
H
,
Sudarshan
TS
.
Basal plane dislocation conversion near the epilayer/substrate interface in epitaxial growth of 4° off-axis 4H–SiC
.
J Cryst Growth
2013
;
371
:
94
101
.
37.
Zhang
Z
,
Moulton
E
,
Sudarshan
TS
.
Mechanism of eliminating basal plane dislocations in SiC thin film by epitaxy on an etched substrate
.
Appl Phys Lett
2006
;
89
:
081910
.
38.
Ohno
T
,
Yamaguchi
H
,
Kuroda
S
, et al 
Influence of growth conditions on basal plane dislocation in 4H-SiC epitaxial layer
.
J Cryst Growth
2004
;
271
:
1
7
.
39.
Yang
L
,
Zhao
LX
,
Wu
HW
, et al 
Characterization and reduction of defects in 4H-SiC substrate and homo-epitaxial wafers
.
Mater Sci Forum
2020
;
1004
:
387
392
.

Lixia Zhao (1969– ), female, PhD. She has long been engaged in the semiconductor materials growth of Si and SiC. At the same time, she hosted and participated in several projects of national and provincial, such as industrialization of large diameter silicon epitaxy, industrialization of single crystal polishing wafers and epitaxy for SiC.