Silicon field-effect transistors (FETs) were developed in the late 1950s as a scaled-down, energy-efficient substitute for bipolar junction transistors. They paved the way for the high-density integrated circuits that today underlie most electronics (see the article by Alan Fowler, Physics Today, October 1993, page 59). With their lower gate voltages, carbon nanotube FETs could surpass silicon FET energy efficiency by nearly a factor of 10. In 2013 Subhasish Mitra, Max Shulaker (then at Stanford University), and coworkers made the first CNFET microprocessor; it comprised 178 transistors and could run a single operation.
Variability caused by the production process has made moving beyond that proof-of-concept computer challenging. Gage Hills, Christian Lau, and coworkers in Shulaker’s group at MIT have now overcome that hurdle with a protocol for wafer-scale CNFET microprocessor production. Their technique is also compatible with existing CMOS infrastructure, which lowers the bar for future commercial implementation.
To remove carbon nanotube aggregates—a common contaminant from CNT deposition on silicon wafers—the researchers spin-coated a layer of adhesive polymer over the device and then removed the aggregates using ultrasonic vibrations. In previous attempts, sonication damaged the nonaggregated CNTs. Using the photoresist binds them to the wafer, which preserves their function while removing more than 99% of the aggregates.
CNFET circuits require both n- and p-doping, and past doping techniques produced high variability, which limited reproducibility. The new process developed by the MIT researchers uses atomic-layer deposition to encapsulate the CNTs in an oxide layer. They precisely choose the stoichiometry of that layer such that it electrostatically dopes the CNTs and tunes the gates’ threshold voltages.
There researchers had one problem they couldn’t avoid: About 0.01% of CNTs produced in typical syntheses are metallic instead of semiconducting. Normally that would be enough to interfere with the operation of a CNFET chip’s logic gates, but the authors found a workaround through clever circuit design. Metallic CNTs are more problematic at certain points in sequential logic operations, so the processor uses only combinations of gates that perform well despite their metallic contamination.
The 16-bit wafer-fabricated RV 16X-Nano microprocessors, shown in the pictures, each contain more than 14 000 CNFETs and can run compiled code. The developers of the new manufacturing methodology hope that this technique lays the groundwork for large-scale commercial production and implementation of CNFETs. (G. Hills et al., Nature 572, 595, 2019.)
