Part B: Imaging dielectric properties of Si nanowire oxide with conductive atomic force microscopy complemented with femtosecond laser illumination Available to Purchase

Si nanowires (NWs) are being considered and tested for a range of exciting applications in nanoelectronics, including memory, logic gates, single electron transistors [1], optoelectronic devices [2] and sensors [3]. Particularly relevant to this work are non-volatile memory applications, such as Silicon Nanowire based memory on Semiconductor-Oxide-Nitride, SONOS [4], for which tunneling through the dielectric is part of normal operation. The specifications and reliability of these devices relate to the surface structure of the NWs and to the properties of the oxide sheath which is called to play the role of gate dielectric [5, 6]. Structures such as wraparound gate transistors [7] or core-shell heterostructures [8] require good control of the wire surface, in order to achieve uniform cross section and to minimize carrier scattering at rough interfaces. Equally important are the charge transport properties of the oxide which may be affected by surface irregularities. Current through planar gates grown on Si wafers and, particularly, the effect of Stress Induced Leakage Current (SILC) have been the subject of a vast body of experimental research and models proposed [9-11]. On the other hand, little is known about SILC and related phenomena in Si NW based MOS devices. As pointed out by Vogel [12], these are likely to continue controlling future transistors fabricated by technologies beyond microlithography on wafers and it is important to find new and complementary ways for their characterization.