The International Technology Roadmap of Semiconductors (ITRS) plans to introduce in production 65nm node CMOS devices by 2007. These devices will require source and drain extensions depth in the 10nm range. More of this, 20 to 40 nm deep contact heavily doped source and drains as well as abruptness of 2 nm/decade will be needed.
Today no known solutions are available to achieve such shallow extensions holding sheet resistance of 120 to 450 ohms/square.
To achieve these requirements, the use of Laser Thermal Processing (LTP) is the challenging approach to the conventional Rapid Thermal Processing (RTP).
Excimer laser with highly absorbed UV light by silicon and high energy per pulse induce a fast and controlled melting and solidification process. Indeed the ramp up and down times in the order of hundreds of nanoseconds enables very shallow junction depth, very abrupt profiles and a solubility limit higher than those usually encountered with conventional RTP.
Another benefit, the low thermal budget of this technique offers the possibility to suppress TED (Transient Enhanced Diffusion).
In this paper we shall emphasis on the use of a Very Large Excimer Laser that allows annealing of a full die in a single spot (4 cm² at once). Preliminary results in term of activation depth measurements will be presented.