Simulation of plasma‐etched lithographic structures

The resist development model has been extended to simulate etched images in semiconductor processing. The model has been used to simulate under a variety of conditions varying from conventional wet etching to newer directional etching processes such as dry etching. As compared to the conventional wet etching processes the dry etch technologies erode the resist mask more intensively during processing. The model has been confirmed using a number of experimentally alterable and lithography‐dependent conditions such as etch rates, resist profiles, resist thicknesses, etc. The effects of these on the final image shapes and the image sizes are predicted by simulations and aid the process definitions minimizing multivariate experiments. Isotropic etch processes such as those in the high‐pressure reactors are also modellable by this approach.