We study here the fabrication of p-channel MOS field effect transistors with 4 μ gate lengths, made with electron-beam lithography substituted for conventional photolithography. The remainder of the processing included tungsten metallization with self-aligned ion implanted source and drain regions as described by Moline et al., and by Boll and Lynch (IEDM, 1972). The resulting transistors were characterized by turn-on voltage, Vt of 1.3–1.6 V (〈0100〉 orientation) and 1.8–2.1 V 〈111〉. For the 〈100〉 devices, the distribution in Vt across each slice was very tight (2σ < 0.1 V). The experimental values for Vt could be predicted from independently measured values of substrate doping and flatband voltage. Transconductance per square of gate was typically ∼ 14 ± 1.4 μʊ(i.e., μΩ−1) (at VG–Vt=−3V) for devices with a gate oxide thickness of 1000 Å and a gate width of 200 μ. The value for mobility, μ, for the 〈100〉 devices was estimated to be 160 cm2V−1sec−1. The punch-through voltage was 23 ± 1.5V. The bias-temperature stability of the resulting devices was found to be strongly dependent on the crystal orientation. Slices with 〈100〉 faces were highly stable (<0.08 V shift after five minutes of positive or negative application of 106V/cm at 300 °C); slices with 〈111〉 orientation were considerably less stable (up to 0.7V shift under the same conditions). The results are in general accord with previous results using conventional photolithography projected to account for narrower gate lengths. They indicate that no additional complications were introduced by the substitution of electron-beam lithography.

This content is only available via PDF.
You do not currently have access to this content.