Self-aligned fabrication of vertical, fin-based structures

Patterning of semiconductor devices has typically been a two-dimensional (2D) process. Since 2D patterns transfer best to flat surfaces, “planar processing” has been the primary design goal throughout most of micro- and nanofabrication’s history. Traditionally, this has meant that fabrication is “bottom-up” because the material furthest from the surface must be deposited first when there is only access to the top of the wafer.

As we have progressed toward more advanced device designs, tricks can be played that utilize various combinations of directional or conformal depositions and anisotropic or isotropic etches to overcome resolution limits using nonplanar surfaces. An example of this can be found in sidewall-assisted double pattering where sidewall growth is used to create subresolution patterns.^1,2

Within the field of power electronics, designers of semiconductor devices have found that a vertical design offers better control of the electric field, allows for improved current confinement, and provides area-independent breakdown voltages. Examples of such devices include the current aperture vertical electron transistor,^3,4 the trench-MOSFET,^5,6 and the junction field-effect transistor.⁷ However, given the prevalence of planar-processing techniques and tools, many of these devices are actually planar designs with a turn in the current path to transition to vertical current flow. Conversely, the vertical GaN FinFET⁸ is a truly vertical device where all the electrodes are stacked on top of one another with the source and gate metals patterned along the sidewall of a narrow fin. Patterning along a sidewall means that standard planar photolithography techniques cannot be used. Instead, the most common fabrication approach is to use a lithography-free, etch-back process where the surface is planarized with a spin-on resist and then carefully etched back to reveal the tops of the fins, which are subsequently etched using the resist as a mask.^8–11 

While a resist-based etch-back approach works on small prototypes, it is difficult to scale and often has poor yield. As we see in Fig. 1, spin-on planarization over a patterned surface is rarely truly flat. Surface tension, edge effects, and curing shrinkage all contribute to a nonideal surface, which when etched back reveals different portions of the fin array.^12,13 For large area devices, the variation in resist thickness can lead to complete device failure.

An alternate approach uses the same “planarize”–“etch-back”–“etch” approach, but substitutes plasma-enhanced chemical vapor deposition (PECVD) of $SiO 2$ for spin-on resist. With thick enough conformal coating of oxide, the surface becomes locally planar, which then allows for a uniform etch back.^14,15 Unfortunately, two problems remain: (1) deep etch-backs through dry etching of $SiO 2$ is a potentially damaging process that incorporates fluorine ions into the source region (which degrades contacts in GaN devices), and (2) the process is still “bottom-up,” meaning that the gate oxide and the gate metal must be deposited before the source metal. A gate-first process prevents a high-temperature anneal of the source contacts due to the lower thermal budget of the gate oxide, which can limit contact resistance.^16,17

To overcome these issues, this article will present how a seldom-used technology, angled evaporation, can be used for self-aligned fabrication of vertical, fin-based devices. While the discussion will focus on GaN based devices, such as the vertical GaN finFET or high-aspect ratio fin diodes, the fabrication principles are applicable to any other devices and materials with fins patterned into the surface.

This report will first focus on the theory and design methodology for creating self-aligned fin-based structures. Then, two examples are presented that demonstrate how this technology has been used to fabricate highly complex structures that are not possible with standard, planar-processing techniques.

Electron beam evaporation is a highly directional deposition method that is compatible with many metals and some oxides. Angled evaporation simply places the sample at an angle relative to the path of the incoming material.¹⁸ By tilting our sample, we can use patterned structures to create shadows on the surface where material cannot be deposited. This technique has been used to fabricate photonic structures¹⁹ Josephson-junctions,²⁰ and has even been used to fabricate the gate for vertical finFETs²¹ and nanowire FETs,²² although the nanowire FETs relied on self-shadowing effects instead of adjacently pattered features. In this section, we will show how multiple depositions at varied angles and thicknesses can be used to take this technique a step further and fabricate more advanced structures that are not possible with standard lithography techniques.

Our method relies on periodic fin arrays, which let us easily control the shadows made through angled evaporation and use them to our advantage. Two essential building blocks for device design are the “mushroom structure” and the “sidewall structure,” which are depicted in Fig. 2. For the mushroom structure, material will only be patterned along the top of a fin, while for a sidewall structure, material will only be patterned along the sidewall of the fin and base of the trench. To create each structure, we will tilt the sample and vary the metal thickness so that our fins remain as symmetrical as possible; however, varied thickness and metal choices can be used for even more complex designs.

To tilt our samples to arbitrary angles, we created a custom mount that fits in a standard 6-in. wafer holder. This mount, shown in Fig. 3, is compatible with any electron beam evaporation system that is set up for lift-off processes. To accurately set the angle, we utilize a digital angle finder and a 3D printed alignment jig. While the digital angle finder’s reported accuracy of $± 0.1 °$ is more than accurate enough for device development, once the process design is finalized, rigid custom mounts could be fabricated for each step to improve repeatability and yield.

With a mushroom structure, we showed how we could pattern material along the top of a fin. If, however, we want material along the sidewall of a fin, we can start with the mushroom structure and then use the newly formed overhangs that we created with the deposited material to cast shadows along the sidewall for additional depositions. This is illustrated in Fig. 5 where a small shadow can be seen beneath the light gray metal in the zoomed-in image.

To keep the gap distances symmetric, we do not need to account for the additional height and width changes on the fin from the first deposition because we are only using the overhang created from the mushroom, which is shadowed during the first deposition. If we want identical sidewall thicknesses for the metals, we use the same relation in Eq. (3); however, the thickness of metals and the distance they extend along the bottom of the trench, $d t$⁠, will not be symmetric. In order to coat the entire bottom of the trench, multiple depositions of increasingly reduced angles (or a continuously rocking deposition) should be used to cover the gap. Due to the large number of design variables, several iterations may be required to calculate a desired sidewall geometry, which can be readily automated in a spreadsheet or simulated with an appropriate software.²³ 

Finally, if a metal is wanted exclusively along the fin sidewall, the mushroom structure can be undercut so that we lift off the metal on top of the fins. This will be further explained in Sec. III.

To show the versatility and accuracy of this technique, we will present several examples.

As noted in Sec. I, the ideal vertical finFET process is source-first and self-aligned—both of which are possible using angled evaporation techniques.

The first step in our finFET fabrication is to pattern fins using electron beam lithography and dry etch them into the surface. We then must pattern an oxide spacer along the bottom of the fin. This is crucial to prevent premature breakdown of the gate due to the enhanced electric field at the corner of the trench.⁸ To begin the process, we deposit a thin, conformal layer of $SiO 2$ over the fins, which will be masked with a sidewall structure made of Ni. When calculating deposition angles, we simply reduce the trench width by the thickness of the oxide on each side of the fin. To make the etch mask, we first use Al to form a mushroom structure with an $h m$ such that Ni can be used as the sidewall metal with the edge extending up the fin by approximately 100 nm [Fig. 6(a)]. The choice of Al for the mushroom metal is important because we can etch it away with a tetramethylammonium hydroxide (TMAH) based developer, which has a very high selectivity to GaN, Ni, and $SiO 2$ [Fig. 6(b)]. This undercuts the metal on top of the fins, which just leaves an Ni etch mask along the bottom of the fin [Fig. 6(c)]. Finally, we can etch the exposed $SiO 2$ with a gentle, isotropic dry etch and clean the sidewall residue with a dilute buffered oxide etchant dip before stripping the Ni mask with an Ni etchant [Fig. 6(d)].

With our source-first process, we then deposit the Ti/Al source metal using a mushroom structure along the top of the fin, which is depicted in Fig. 7(a). After this stage, the contacts can be annealed without damaging the gate oxide.

Once the source metal is complete, we use atomic layer deposition to deposit the $Al 2 O 3$ gate dielectric before completing the sidewall structure with our Ni gate [Fig. 7(b)]. The gap distance is chosen to be as small as possible while still ensuring that the Ni metal is discontinuous between the sidewall and mushroom structures. This source-first process offers another distinct advantage—with the gate oxide between the source contact and the gate metal, it is impossible for a gate-source short to form.

Finally, to finish the process, we deposit a thick spacer oxide with PECVD $SiO 2$ and etch vias to expose the tops of the fins. We then use an Ni etchant to remove the Ni on top of the fins without fear of overetching due to the discontinuity between the top and sidewall gate metals. The $Al 2 O 3$ also acts as a good etch-stop to protect the source metal during this etch. After removing the Ni, the $Al 2 O 3$ is dry etched away to expose the source. Outside the fin array, we etch a via down to the gate pad and pattern our pad metal on the top and backside of the wafer.

The completed structure is presented with a corresponding scanning electron microscope (SEM) image taken in a dual-beam focused ion beam (FIB) microscope in Fig. 8. Using these techniques, we readily achieved submicrometer gate lengths with a self-aligned gate-source spacing of under 50 nm without any limitations due to lithographic alignment or resolution requirements. Figure 9 shows a representative output and transfer characteristics for a fabricated vertical GaN finFET showing ohmic turn-on and low gate leakage.

Superjunctions are a class of power devices that utilize a two-dimensional structure along the current path to better control the electric field within the device and achieve a superior breakdown voltage (⁠ $V B$⁠) and specific on-resistance (⁠ $R on , sp$⁠). A distinctive attribute of superjunctions is periodic arrays of high-aspect ratio pillars that alternate between either p- and n-type materials or a semiconductor and high- $κ$ dielectric.^24,25 A common approach to form the alternating pillars is to etch fins into the surface, then either deposit, regrow, or implant the space between the fins. For Si, deep, high-aspect ratio etching is commonplace with the invention of the deep reactive ion etching (DRIE). Unfortunately, in material systems such as GaN, such an etching process does not exist. The few examples of GaN superjunctions demonstrated in the literature have used sputtered NiO as the p-type material. In these devices, the trench widths needed to be wide enough to ensure adequate sidewall coverage deep in the trenches, and the fin widths had to be wide enough to be patterned and etched in a single step.^26,27 These trade-offs for fabrication come at the expense of ultimate device performance. In this section, we will describe how using angled evaporation can achieve record high aspect-ratio fins in GaN for superjunction and related applications.

To begin our etch process, we pattern a hard mask using electron beam lithography and Ni lift-off [Fig. 10(a)]. We have found that our GaN etch has a 20:1 selectivity to Ni; therefore, we use 50 nm of Ni to pattern 1  $μ$m tall fins. Using a thin mask is important to achieving fins with widths in the 100–500 nm range. Using a thicker Ni mask would enable deeper etching, but the patterning at high resolutions becomes far more difficult, if not impossible. After dry etching the fins, we use a 1 h hot (⁠ $80 ° C$⁠) TMAH wet etch to smooth the sidewalls of the fins and then strip the Ni mask with an Ni etchant and a piranha clean.²⁸ 

With fins patterned in the wafer, the deep etching continues in a cyclical process of masking and etching, which is similar to the Bosch process used for DRIE. The main steps of this process are shown in Fig. 10(b). To begin the cycle, we use angled evaporation to redeposit the Ni mask using as shallow of an angle as possible to keep the metal on top of the fins thick while the sidewall metal remains thin. In this step, the angle should be chosen to ensure that nothing is deposited at the base of the trenches. After depositing the metal from both sides of the fins, we use a dry etch to deepen the trenches. Again, we smooth the sidewalls using a hot TMAH wet etch and strip the mask. The cycle then repeats until we achieve the desired etch depth. As the fins get taller, the deposition angle can be reduced without the risk of depositing at the base of the trenches, which allows for thicker remasking layers and deeper etches to speed up the process. For cases where the trenches are different widths, the angle should be chosen based on the widest trench.

The final top-side contacts are formed through another mushroom structure once the desired fin depth is achieved. This prevents the need for any remasking on very narrow features [Fig. 10(c)].

Using this process, we have demonstrated high- $κ$ fin diodes with aspect ratios as high as 26:1. The performance of these devices will be presented in a future publication.²⁹ A cross-sectional SEM confirming the device fabrication is presented in Fig. 11. Without fabricating devices, we have also demonstrated much higher aspect ratio fins; however, these thin fins require additional support to prevent unintentional bending. Figure 12 shows a cross-sectional SEM of fins with an aspect ratio approaching 70:1, which, to our knowledge, is the highest aspect ratio for etched fins in GaN reported to date.

Recent interest in vertical and stacked device designs have challenged the traditional approach of planar processing in semiconductor manufacturing. In this article, we have presented the design methodology of fabricating self-aligned, vertical, fin-based structures along with several applications. By utilizing the seldom-used technique of angled electron beam evaporation, we demonstrate how submicrometer features can be patterned along vertical sidewalls while avoiding any lithography based limitations. Using a readily fabricated mount, any evaporator setup for lift-off can be used to explore these fabrication techniques.

The application space for this technology includes the self-aligned vertical finFETs and high-aspect ratio fin etches that were discussed above, and it has already been successfully used for both field emitter arrays with integrated anodes³⁰ and optically controlled vertical GaN finFETs.³¹ While the discussion has focused on GaN, applications extend to any material where fins can be etched into the surface. By increasing the number of depositions or creating intentional asymmetries, even more intricate structures can be fabricated. Additionally, by combining the mount’s angle rotation with a programmable motor and coordination with the evaporator’s shutter, smoother layers with varied thickness profiles can be fabricated without having to vent the process chamber multiple times. For large wafer manufacturing, thickness uniformity can be maintained through properly designed sets of uniformity correction masks designed for each angle used in the process.³² 

These processes and techniques show an interesting and novel approach to enable a wide variety of new device architectures and improve yield in existing designs.

This material is based upon the work supported by the Department of Energy, Office of Science, Office of Basic Energy Sciences under Award No. DE-AR0001591.

The authors have no conflicts to disclose.

Joshua Perozek: Conceptualization (lead); Data curation (lead); Formal analysis (lead); Investigation (lead); Methodology (lead); Validation (lead); Visualization (lead); Writing – original draft (lead); Writing – review & editing (equal). Tomás Palacios: Conceptualization (equal); Funding acquisition (lead); Methodology (supporting); Supervision (lead); Writing – original draft (supporting); Writing – review & editing (supporting).

The data that support the findings of this study are available from the corresponding author upon reasonable request.