Vertical silicon nanowedge formation by repetitive dry and wet anisotropic etching combined with 3D self-aligned sidewall nanopatterning

Three-dimensional (3D) stacking of nano-devices is an alternative approach to increase the areal density where traditional lateral downscaling of electron devices encounters fundamental, practical, or economic limits. A good example where such an approach has been applied is for nonvolatile flash memory applications such as in vertical NAND (V-NAND), also known as 3D-NAND.^1–3 In 3D-NAND, the flash memory cells in a chip die are stacked vertically to increase storage density. This stacking is achieved by the use of plasma processing.

Plasma processing provides process flexibility, but it remains challenging to minimize plasma induced sidewall damage during etching in stacked layers⁴ or in high aspect ratio trenches in silicon (Si).⁵ By combining dry etching and wet anisotropic etching in single-crystalline Si, it is possible to achieve well-defined geometries by taking advantage of the slow etching {111} Si planes with smooth surfaces which can serve as templates for further processing.^6,7 Self-aligned techniques, such as corner lithography^8,9 and edge lithography,^10–12 allow submicron patterning without the additional use of expensive or complex lithography techniques. Wet anisotropic etching of Si and corner lithography have been applied to fabricate 3D fractals,^13,14 3D nanowires and nanoapertures,^9,15,16 and fluidic components.¹⁵ The use of both dry and wet etching of Si has shown the possibility to produce high-aspect ratio octahedra and donutlike structures,¹⁷ nanopillar confined tunnel junctions,¹⁸ sigma shaped source/drains for metal-oxide-semiconductor field-effect transistors (MOSFETs) to enhance device performance,^19,20 and vertically stacked inverted triangular and diamond-shape Si nanowires.²¹ 

Based on crystallographic defined Si nanowedges, previous work has shown the successful fabrication of 3D crystalline Si nanostructures,²² massive parallel NEMS flow restriction nanoslit arrays,²³ and self-aligned wedge multiplication by convex corner lithography.²⁴ In this work, we demonstrate a novel wafer-scale technology to create vertically stacked Si nanowedges and 3D sidewall patterning. Both concave and convex corners of the vertically stacked nanowedges can be accessed in a self-aligned manner for further processing through sidewall patterning. The horizontally (a) and vertically (b) oriented Si nanowedges, and 3D sidewall patterning (c) are illustrated in Fig. 1. The geometries are defined by the {111} Si planes and intersect each other at 70.6° or 109.4°. Displacement talbot lithography²⁵ (DTL) is utilized to produce wafer-scale periodic nano lines in combination with iterative dry and wet etching to create vertically stacked nanowedges [Fig. 1(b)]. The concave corners of the vertically stacked nanowedges are accessed to form rhombus-shaped structures [Fig. 1(c)]. Vertically etched nanowedges have previously allowed for Si nanowire formation,²¹ but not at the sub-200 nm scale or for sub-20 nm sidewall patterning as reported in this work. This technology platform enables the 3D fabrication of high-density nanodevices for, among others, electronic, fluidic, magnetic, and plasmonic applications.

Throughout all experimental steps involving wet-chemical processing, substrates undergo standard cleaning in a quick dump rinser (QDR), where de-ionized water (DI) is used to rinse chemicals until a resistivity of 10 MΩ is reached. The substrates are subsequently dried in a single-wafer spinner at 2500 rpm for 60 s, with a 45 s nitrogen purge included.

A schematic overview of the fabrication steps of wafer-scale vertically stacked Si nanowedges is illustrated in Fig. 2.

For these experiments, boron doped ⟨100⟩ Si substrates with a resistivity of 5–10 Ω cm were selected (100 mm in diameter, 525 ± 25 μm thick, single side polished, Okmetic, Finland). Note that processes conducted at room temperature are carried out at 20 °C. The substrates are standard prefurnace cleaned with a fuming nitric acid (HNO₃) solution (99 wt. %, room temperature, 2 × 5 min in separate beakers) and boiling HNO₃ solution (95 °C, 10 min), followed by native oxide etching in a hydrofluoric acid (HF) solution (1 wt. %, room temperature, 2 min, Micropur VLSI, Technic, France). Low pressure chemical vapor deposition (LPCVD) is then performed to grow conformally an approximately 101 nm thick stoichiometric silicon nitride (Si₃N₄) layer (800 °C, 200 mTorr, 22 SCCM SiH₂Cl₂, 66 SCCM NH₃, 90 min, TS6604, Tempress).

The alignment of the lithography mask pattern in the Si ⟨110⟩ direction is achieved with an accuracy of 0.05° using “Vangbo” structures.²⁶ A precise alignment minimizes over-etch and avoids steps or terrasses formed on the Si {111} planes causing rough surfaces.^27–29 DTL²⁵ has been carried out to create wafer-scale periodic nanoline patterns of about 240 nm wide with a pitch of 500 nm. First, a ∼180 nm thick bottom antireflection coating (BARC, AZ Barli-II 200) is spin-coated at 3000 rpm for 45 s and prebaked at 185 °C for 60 s. On top of the BARC layer, a ∼160 nm thick positive tone i-line photoresist (PR) [1:1 PFI: PGMEA (propylene glycol monomethyl ether acetate, provided by Sumitomo Chemical Co., Ltd., Japan)] layer is then spin-coated at 2000 rpm for 45 s and prebaked at 90 °C for 60 s. The exposure of the PR is carried out utilizing a 365 nm UV laser source for 75 s at an intensity of 0.98 mW cm⁻², a Talbot distance of 10 μm, and a gap spacing of 75 μm (PhableR 100C, Eulitha, Switzerland). After exposure, the substrates are baked at 110 °C for 60 s followed by development of the PR in a solution of TMAH (OPD4262, Arch Chemicals, 2 × 30 s in separate beakers).

After DTL, the PR is directionally transferred into the underlying BARC layer [Fig. 2(a)] using a nitrogen plasma in a conductively coupled plasma reactive ion etching (CCP-RIE) system (25 W, 10 mTorr, 50 SCCM N₂, 8 min 30 s, DC bias ∼270 V, TEtske, homebuilt at MESA+).³⁰ Prior to the RIE of the BARC layer, the plasma chamber is cleaned by wiping with acetone, followed by standard oxygen plasma cleaning (50 SCCM O₂, 50 mTorr, 100 W, 10 min). In the same CCP-RIE system, the underlying Si₃N₄ layer is etched using a fluorocarbon-based etchant (25 W, 10 mTorr, 25 SCCM CHF₃, 5 SCCM O₂, 5 min, DC bias ∼240 V, TEtske, home-built at MESA+). The substrates were then dipped in an HF solution (1 wt. %., room temperature, 30 s) to etch the native oxide on the exposed Si. Next, the substrates are transferred to the inductively coupled reactive ion etching (ICP-RIE) system to anisotropically etch the exposed Si (Plasma Pro 100 Estrelas, Oxford instruments, United Kingdom). A continuous mixed mode of sulfur hexafluoride (SF₆) and octafluorocyclobutane (C₄F₈) is used for etching and passivating, respectively, to achieve smooth and vertical sidewalls of about ∼130 nm (18 mTorr, 48 SCCM C₄F₈, 23 SCCM SF₆, 41 W CCP, 800 W ICP, 0 °C substrate temperature, DC bias ∼202 V, 20 s).³⁰ The substrates are then in situ cleaned in the same chamber to remove fluorocarbon residues and PR/BARC [Fig. 2(b)] using an oxygen plasma (100 SCCM O₂, 10 mTorr, 2000 W ICP, 0 °C substrate temperature, 3 min) followed by extra cleaning in HNO₃ (99 wt. %, room temperature, 10 min) and RCA-2 (mixture solution of HCl:H₂O₂:H₂O at ratio 1:1:5, 80 °C, 15 min). Next, the substrates are transferred to an HF solution (1 wt. %, room temperature, 30 s, Micropur VLSI, Technic, France) to etch the native oxide from the exposed Si. Then it is directly transferred to a potassium hydroxide (KOH) solution (20 wt. %, 20 °C, 10 min, pellets Emplura, Merck KGaA, Germany) to etch Si anisotropically to create rhombus-shaped structures confined by the Si {111} planes [Fig. 2(c)]. After the KOH step, the substrates are RCA-2 (mixture solution of HCl:H₂O₂:H₂O at ratio 1:1:5, 80 °C, 15 min) cleaned to remove alkali ion residues from the KOH solution.

Next, the substrates are prefurnace cleaned in ozone steam (home-built at MESA+, Semozone 090.2 lP Ozone Generator). The cleaning takes 40 min which includes twice cleaning in ozone steam for 5 min (120 °C, ozone 2 L/min, 1.3 bars) followed by in situ rinsing in DI water and drying. The formed thin chemical oxide layer during the ozone steam cleaning is etched in HF solution (1 wt. %, room temperature, 2 min). Then the substrates are directly transferred to the furnace to perform a LOCOS step to grow about 5.7 nm thick dry thermally grown silicon dioxide (SiO₂) layer [Fig. 2(d)] on the slanted Si {111} planes (800 °C, 30 min). Next, the substrates are transferred to the ICP-RIE system (Plasma Pro 100 Estrelas, Oxford Instruments, United Kingdom) to etch directionally into the Si [Fig. 2(e)] to open the concave corners for further processing (18 mTorr, 48 SCCM C₄F₈, 23 SCCM SF₆, 41 W CCP, 800 W ICP, 0 °C substrate temperature, DC bias ∼202 V, 18 s). It is worth mentioning that the etching time is short enough to avoid complete etching of the SiO₂ from the (111) surface and thinning of the Si₃N₄ layer from the top (100) surface. Next, the substrates are in situ cleaned in an oxygen plasma followed by RCA-2 cleaning. Then they are shortly dipped in an HF solution to remove the native oxide from the concave corners (1 wt. %, room temperature, 10 s). It is worth noting that, during directional RIE the stacked nanowedges act as shadowing mask so that the SiO₂ mask remains intact prior KOH while it is removed from the surroundings. See Fig. S1 in the supplementary material for more details. The exposed Si at the concave corners is timed etched in KOH [Fig. 2(f)] to create nanowedges (20 wt. %, 20 °C, 30 min). Then, the substrates are RCA-2 cleaned, followed by ozone steam cleaning (40 min), and SiO₂ layer stripping [Fig. 2(g)] in HF (1 wt. %, room temperature, 2 min). The fabrication steps in Figs. 2(e) and 2(f) are repeated to create second [Fig. 2(h)] and third [Fig. 2(i)] vertically stacked nanowedges.

The schematic fabrication process of the sidewall patterning of the vertically stacked nanowedges is presented in Fig. 3. After the process iteration steps indicated in Figs. 2(d)–2(f) to form three stacked nanowedges [Fig. 3(a)], the substrates are prepared for corner lithography [Figs. 3(b) and 3(c)].

First, the substrates are ozone steam cleaned (40 min) followed by a post-HF dip (1 wt. %, room temperature, 2 min) to remove the thin chemical oxide layer that forms during this cleaning process. They are then directly transferred to the furnace to deposit conformally about 26 nm Si₃N₄ using LPCVD (800 °C, 200 mTorr, 22 SCCM SiH₂Cl₂, 66 SCCM NH₃, 33 min, TS6604, Tempress). Next, the deposited Si₃N₄ layer is isotropically timed etched in a hot phosphoric acid (H₃PO₄) solution (85 wt. %, 125 °C, 78 min), resulting in Si₃N₄ remaining only at the concave corners [Fig. 3(c)]. An over-etch factor of 1.12 is applied at an etch rate of 0.4 nm/min to ensure complete etching of Si₃N₄ on the slanted planes.

Next, the substrates undergo a second ozone steam cleaning (40 min), followed by an HF dip (1 wt. %, room temperature, 1 min) to strip the formed thin chemical oxide layer. A LOCOS step is carried out [Fig. 3(d)] using dry thermal oxidation to grow about 6.8 nm SiO₂ (800 °C, 75 min) on the (111) surface outside the concave corners. Subsequently, the substrates are UV-ozone treated to enhance wettability (5 min, UV-Ozone Photoreactor PR-100, UVP Inc., USA) followed by an HF dip (1 wt. %, room temperature, 13 s) to etch the native oxide. The remaining Si₃N₄ layer at the concave corners is then isotropically etched [Fig. 3(e)] in a hot H₃PO₄ solution (85 wt. %, 125 °C, 35 min). Over-etching is applied to ensure complete etching of the Si₃N₄ layers from the concave corners.

Subsequently, the substrates are dipped in an HF solution (1 wt. %, room temperature, 26 s) to etch the native oxide. The concave corners are timed etched in a KOH solution (20 wt. %, 20 °C, 17 min) to create rhombus-shaped cavities [Fig. 3(f)]. Then, the substrates are RCA-2 (mixture solution of HCl:H₂O₂:H₂O at ratio 1:1:5, 80 °C, 15 min) cleaned.

Finally, both the SiO₂ and Si₃N₄ layers are stripped [Figs. 3(f) and 3(g)] in HF (50 wt. %, room temperature, 2 min). The new sharp corners and edges that are created [Fig. 3(h)] can be used as a template for successive self-aligned device fabrication.

Cross-sectional images of the fabricated structures were obtained by cleaving Si substrates along the ⟨110⟩ direction and inspecting them with a scanning electron microscopy (SEM) tool (JSM 7610FPlus, JEOL) at 5 kV or 15 kV. A SEM image after directional RIE of Si is shown in Fig. 4(a). The vertical sidewalls correspond to (110) surfaces while the bottom part is the (100) surface. The roughness on the sidewalls is clearly visible due to lithography and RIE step. The measured etched depth, spacing between sidewalls, and Si width is 127, 260, and 242 nm, respectively.

After anisotropic etching of Si in KOH, a rhombus-shaped geometry was obtained by the slow etching Si {111} planes [Fig. 4(b)]. The sidewall surface is smoothened out and the geometry is confined by (111) surface with well-defined angles. Prolonged KOH etching resulted in an undercut of the Si₃N₄ mask, enlarging the initial mask opening from approximately 260 nm. Consequently, the Si width was reduced to around 202 nm, while the Si₃N₄ mask width remained approximately 242 nm. The measured depth of the rhombus-shaped structure is about 275 nm, and the small undercut is about 42 nm.

The iteration process including dry thermal oxidation, RIE, and KOH etching of Si is shown in Figs. 5(a) and 5(b). The SEM cross-sectional images show the successful formation of the first vertically stacked nanowedges. By repeating the iteration twice, the second vertically stacked nanowedges are formed [Fig. 5(c)]. After three iterations, the third stacked layer of nanowedges can be seen in Fig. 5(d). Note that, during the RIE also the Si₃N₄ mask is etched (∼92 nm/min) such that the initial mask thickness allows for three iterations. To increase the number of iterations, the mask selectivity should be increased and/or the initial Si₃N₄ layer thickness should be increased depending on the desired number of iterations. The mask selectivity can be enhanced by changing the RIE parameters. Moreover, the SiO₂ thickness grown during dry thermal oxidation introduces rounding of the concave corners. Since this rounding increases after each iteration, the thickness should be kept at a minimum to consume less Si. Rapid thermal oxidation (RTO) is often used in the semiconductor industry to have better process control over thin oxides and can be applied here to grow thin oxides.

Given the high selectivity of the KOH solution used in terms of crystal plane selectivity and selectivity with respect to SiO₂,³¹ the vertical wedge periodicity is mainly determined by the directionality of the RIE process, see Fig. S1 in the supplementary material for a more detailed explanation.

A substrate from the same batch containing vertically stacked nanowedges after the third iteration was used to perform sidewall patterning at the concave corners. Corner lithography was carried out by first depositing conformally an Si₃N₄ layer all over the nanowedges, as shown in Fig. 6(a). Subsequently, only Si₃N₄ was left at the concave corners [Fig. 6(b)] by timed etching in H₃PO₄ solution.

The amount of Si₃N₄ in the concave corners depends on the deposited layer thickness and the angle of the corner formed by the {111} Si planes.^8,9,15,16 It is worth mentioning that this substrate [Fig. 6(b)] shows irregularities along the nanowedge depth, i.e., the periodicity of the nanowedge [Fig. 1(b)], compared to the other substrate [Fig. 5(d)] processed from the same batch due to the relatively short etched depth during RIE in the second iteration. These irregularities show that the periodicity can be modified by tuning Si dry etching depth in combination with wet anisotropic etching, though such alterations may not be desirable depending on the application.

A LOCOS step was performed to grow a thin SiO₂ layer on the {111} planes outside the concave corners, as shown in Fig. 7(a). Note that, both the concave corners and the top part of the structures were protected by Si₃N₄ during thermal oxidation. After the LOCOS step, the remaining Si₃N₄ layer at the concave corners was selectively removed in a hot H₃PO₄ solution [Fig. 7(b)]. The Si₃N₄ layer from the top part was thinned down but not completely removed, which is important for subsequent etching.

The substrate was then immersed in a KOH solution to etch Si from the concave corners, as shown in Figs. 8(a) and 8(b). After prolonged etching in KOH [Fig. 8(c)], the rhombus-shaped structures (confined by the slow etching {111} planes) were formed at the concave corners.

The rhombus-shape can serve as an Si template for further fabrication, for instance, by repeating corner lithography, LOCOS, and KOH etching to obtain second generation rhombus-shaped structures. These structures are suitable for subsequent self-aligned 3D patterned thin film processing through thermal oxidation, LPCVD silicon nitride, LOCOS, and corner lithography.^13,14 They also have potential application in the fabrication of electronic devices like curved tunnel junctions.³² 

A novel technology platform has been presented to achieve wafer-scale vertically stacked sub-200 nm Si nanowedges by means of an iterative process of dry etching, wet anisotropic etching, and thermal oxidation. As a proof of principle, vertically stacked nanowedges after three iterations have been obtained. The number of iterations depends on the initial Si₃N₄ hard mask thickness and the etch selectivity between Si and Si₃N₄ during dry etching. The periodicity of the nanowedges can be tuned by Si dry etching in combination with wet anisotropic etching. The etch rate deviation in both dry and wet etching can change the periodicity. The SiO₂ layer, grown on nanowedges during each iteration, causes rounding of concave corners. By minimizing the thickness of the SiO₂ (<6 nm), the rounding effect can be minimized.

The sidewalls of the nanowedges were patterned in a self-aligned manner by means of corner lithography and LOCOS. Only concave corners were opened at sub-20 nm and rhombus-shaped structures have been obtained after etching in KOH. The opening size of the concave corner is adjustable based on the dimensions of the nanowedges and on the amount of masking material left by the timed etching during corner lithography. This platform makes possible the 3D fabrication of high-density nanodevices desired for, among others, electronic, fluidic, magnetic, and plasmonic applications.

See the supplementary material for details on the iterative process for fabricating vertically stacked silicon (Si) nanowedges, including directional reactive ion etching (RIE) of Si, followed by hydrofluoric acid (HF) etching of the silicon dioxide (SiO2) layer, and subsequent anisotropic etching of Si in a potassium hydroxide (KOH) solution.

The authors express their sincere appreciation to the MESA + NanoLab staff for their dedicated efforts in maintaining high standards within the cleanroom facility. This study was jointly supported by the University of Twente and the Max Planck Institute of Microstructure Physics.

The authors have no conflicts to disclose.

Yasser Pordeli: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Céline Steenge: Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Erwin J. W. Berenschot: Conceptualization (equal); Methodology (equal); Supervision (equal); Visualization (supporting); Writing – review & editing (equal). Ray J. E. Hueting: Supervision (supporting); Visualization (supporting); Writing – original draft (supporting); Writing – review & editing (supporting). Andrea Migliorini: Writing – original draft (supporting); Writing – review & editing (supporting). Stuart S. P. Parkin: Funding acquisition (equal); Project administration (equal); Supervision (equal); Writing – review & editing (supporting). Niels R. Tas: Conceptualization (equal); Funding acquisition (equal); Project administration (equal); Supervision (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal).

The data that support the findings of this study are available within the article and its supplementary material.