This paper presents a time- and cost-effective method for the large-area fabrication of photonic crystals with nanometer-scale features on the GaN material. The proposed technique utilizes e-beam lithography and double hard mask layers to enable the high aspect ratio etching of the nanoscale features. The double hard mask layer, which is a photoresist, platinum (Pt) and SiO2, is very strong against plasma etching, making it an effective barrier layer to protect the underlying material during the etching process. The fabricated photonic crystal exhibits a high aspect ratio and excellent uniformity over a large area. This technique can be used for the time-effective production of photonic crystals for various applications such as optical sensing, spectroscopy, and telecommunications. The method presented in this paper can also be extended to other material systems beyond GaN. The proposed approach provides a promising route to achieve the large-area fabrication of nanometer-scale structures with high aspect ratios using e-beam lithography.

Gallium nitride (GaN) is a wide-bandgap semiconductor material with superior electronic properties, making it a promising candidate for various applications such as power electronics, optoelectronics, and high-frequency devices. GaN is known for its higher input powers and superior thermal stability, which enhance its performance in demanding applications.1,2 Its high thermal conductivity, critical breakdown field, mobility, and carrier concentration make it robust for high-performance electronics.3,4 The larger bandgap, higher critical electric field, and switching frequency of GaN facilitate its use in high-power settings.2,5 Additionally, its flexible bandgap and metallic/semiconducting nature contribute significantly to its versatility in various electronic applications.4,6 The high breakdown field, high electron saturation velocity and mobility, and good thermal conductivity of GaN are crucial for its high reliability in power applications.5,7 These features of GaN make it suitable for high-frequency and high-power devices, enabling advanced technological applications.7,8 However, the fabrication of GaN thin films with nanoscale features and high aspect ratios poses significant challenges. One of the major challenges is the etching process, which is critical in creating such features.9 

Traditional etching techniques, such as wet chemical etching and dry etching with plasma, face inherent limitations in achieving precise and uniform nanoscale features with high aspect ratios.9,10 The wet chemical etching process, while effective for bulk material removal, often lacks the required selectivity between different materials. This lack of selectivity can lead to unintended etching of the substrate, causing damage and creating surface roughness. This occurs because the etchants used in wet processes can be nondiscriminatory in their chemical interactions, leading to uneven etching rates and patterns.11,12 On the other hand, dry etching using plasma, such as ion beam etching, reactive ion etching (RIE), and inductively coupled plasma (ICP) etching, although offering better directional control, generates surface damage due to the high-energy ions in the plasma. These ions can sputter or physically displace the material from the surface, causing the creation of sidewall roughness. Additionally, the highly energetic nature of the plasma process can lead to unintended secondary reactions, which further limits the resolution of the features due to the altered chemical composition or physical damage at the etched surfaces.11,12

To overcome these challenges, researchers have explored various alternative techniques providing improved selectivity and control of etching rates, which are necessary for achieving precise and uniform features with high aspect ratios. The study by Cai et al.13 focuses on doping magnetic elements in GaN, highlighting advancements in semiconductor material science rather than directly addressing dry etching challenges. Jeong et al.14 explored the layer-by-layer technique in Through-Silicon Via (TSV) technology, offering solutions for precise control in high aspect ratio structures, a key challenge in dry etching. Niesel and Dietzel15 contribute to microfabrication with their development of microsilicon double mirrors for gyroscopes, indirectly complementing dry etching techniques. Last, Sebbag et al.16 present a bistability mechanism in silicon microring resonators, showcasing innovative approaches in microfabrication that can inform precision and control methods in dry etching processes. However, each of these techniques has its limitations and trade-offs, and the choice of the etching method depends on the specific application and desired feature characteristics. The etch rates and yields are influenced by factors such as ion energy, substrate temperature, and the type of material being etched. Different substrate temperatures result in varying etch rate regimes, which could include sputtering-etch limited, product-resorption limited, and mass-transfer limited regions. Additionally, the etched features showed smooth morphologies with anisotropic sidewalls.17 In the case of etching lithium tantalate, the influence of etch parameters on the etch rate, selectivity, and roughness of the etched patterns was significant. This suggests that precise control over these parameters is crucial for achieving the desired outcomes.18 One limitation specific to ICP etching using HBr chemistry is the occurrence of aspect ratio dependent etching, particularly when the etch aspect ratio of InP reaches 30:1. This indicates a significant challenge in maintaining uniform etching across different aspect ratios.19 

Various etching techniques have been developed to overcome the challenges in achieving precise nanoscale features, but each method comes with its own set of limitations and trade-offs. For instance, dry etching techniques like RIE offer improved control over feature dimensions but can introduce physical damage due to high-energy ion bombardment, impacting material properties and leading to defects in the etched surfaces.20,21 Ion beam etching, while providing excellent anisotropy, often suffers from low etching rates and can result in ion implantation, affecting the electrical properties of the material.21,22 Additionally, the equipment and maintenance for such advanced etching techniques can be cost-prohibitive, limiting their accessibility for certain applications or smaller-scale laboratories.22 These factors necessitate a careful consideration of the specific requirements of the application and the intrinsic properties of the materials being etched, to select the most suitable etching technique. The selection of the appropriate etching method depends on the specific application and the desired feature characteristics.23–25 

E-beam lithography, renowned for its high-resolution patterning capabilities, is integral to nanofabrication processes.26–28 However, when it comes to large-area applications, this technique encounters several notable limitations. The primary hindrance is the slow writing speed, a consequence of the sequential nature of the electron beam scanning process. This low throughput becomes increasingly problematic for complex and high-resolution patterns, as each point in the pattern requires individual attention from the electron beam. This issue is further compounded in larger areas, leading to a proportional increase in the fabrication time.27,29,30

Another significant challenge is the sensitivity of e-beam lithography to substrate charging. In large-area applications, the accumulated charge on the substrate can deflect the electron beam, causing pattern distortions or misalignments. This problem is particularly acute with nonconductive substrates, where charge dissipation is minimal.31,32 Strategies such as the use of conductive coatings can help, but they are not always applicable, especially with certain insulating materials.33 To address these challenges, recent developments have focused on parallelizing the e-beam lithography process. Technologies like multibeam lithography aim to increase throughput by simultaneously writing multiple points or areas, thereby significantly reducing the time required for large-area patterning.34 However, these advanced systems can be costly and complex, limiting their accessibility and practicality for certain applications.35 

Undoped epitaxially grown GaN samples with a thickness of 5–6 μm were used in this study. The GaN layers were grown on double-side polished, prime-grade sapphire substrates measuring 700 μm in thickness. Established techniques for the epitaxial growth of GaN on sapphire include pulsed laser deposition (PLD),36 hydride vapor phase epitaxy (HVPE), and epitaxial lateral overgrowth (ELO),37 chemical vapor deposition,38 ion beam-assisted molecular beam epitaxy (IBA-MBE),39 and high-temperature growth on optimized nucleation layers.40 

As depicted in Fig. 1, the various stages involved in the fabrication process of the gallium nitride (GaN) photonic crystal are presented. To enable the forthcoming patterning process, although it still involves plasma dry etching, a distinctive hard mask layer was deposited onto the GaN surface. This involved the deposition of a 400 nm SiO2 layer using plasma-enhanced chemical vapor deposition (PECVD). Additionally, a 5 nm Ti layer and a 40 nm Pt layer were deposited using an electron beam evaporator. The desired device structure pattern was defined using e-beam lithography. ZEP250 photoresist with a dilution ratio of 1:2 and a thickness of ≈50 nm was spin-coated onto the sample surface, followed by a baking process, which is 5 min at 170 °C. The pattern was then transferred onto the photoresist through e-beam exposure. Subsequently, the pattern was developed to reveal the desired structure.

FIG. 1.

Step-by-step process flow chart for GaN photonic crystal fabrication, illustrating the deposition of individual hard mask layers, sequential etching of each layer, and the resulting final structure.

FIG. 1.

Step-by-step process flow chart for GaN photonic crystal fabrication, illustrating the deposition of individual hard mask layers, sequential etching of each layer, and the resulting final structure.

Close modal

The etch resistance of ZEP resist is insufficient for the etchants typically used on GaN, resulting in rapid degradation during the etching process. This rapid degradation contributes to inaccurate or partial pattern transfer. To realize the desired nanosurface features on GaN, which ZEP resist alone could not achieve, it was essential to introduce additional hard mask layers. By selectively etching these hard mask layers, the pattern was successfully and accurately transferred to the underlying substrates. Subsequently, a selective etching process for these hard mask layers was employed to facilitate the transfer of the pattern onto the underlying substrates. The Pt and Ti layers were etched using a radio frequency (RF)-assisted ICP etching process. The etching was carried out for a duration of 10 min, utilizing a gas mixture of CCl2F2/CF4/O2 (23:10:3). The ICP and RF powers were set at 300 and 25 W, respectively. Similarly, the SiO2 layer was etched for 10 min using an RF-assisted ICP etching process with a gas mixture of CHF3/O2 (40/2 SCCM). The ICP and RF powers for this step were set at 400 and 50 W, respectively. Finally, the ≈5 μm GaN layer was etched to define the final device structure. RF-assisted ICP etching was employed for a duration of 10 min using a gas mixture of Cl2/BCl3/Ar (30/15/5). The ICP and RF powers were set at 400 and 300 W, respectively.

Please note that the etching times for the hard mask layers and the GaN layer were assumed to be the same (10 min) based on the provided information. These values can be adjusted as necessary to achieve the desired results in your experimental setup. This section outlines the growth and fabrication process, including the deposition of hard mask layers, e-beam lithography, and etching steps for both the hard mask layers and the GaN layer.

E-beam lithography employs a precisely concentrated stream of electrons. The electron beam intricately crafts patterns by populating trapezoidal structures with arrays of minuscule dots. Rather than undergoing continuous motion, the beam halts and lingers at specific locations and then takes measured strides before pausing again. Typically, the spacing between the exposed dots is deliberately smaller than the diameter of the electron beam, guaranteeing a consistent dosage throughout the pattern without any perceptible voids.

In the specific scenario of a uniform dot array, it is possible to have a step size significantly larger than the diameter of the electron beam. This leads to an arrangement of isolated dots that are equally spaced from each other. The precise spacing between these dots, known as the dot pitch, is determined by the magnitude of the beam’s step size. Meanwhile, the size of each individual dot is regulated by both the diameter of the electron beam and the duration it dwells at each location. One advantageous aspect of this writing technique is the absence of pattern overhead. Consequently, the total time required for exposure is dramatically reduced. The “dots-on-the-fly” technique proves beneficial when dealing with an arrangement of small dots where the desired dot size closely matches the diameter of the electron beam.41,42 However, in our specific design case, which we targeted to achieve a self-collimating photonic crystal structure,43 we required dots measuring 135 nm, while the electron beam diameter was closer to 20 nm. Increasing the dwell time, in an attempt to compensate, unfortunately, led to distorted dot shapes. Likewise, raising the beam current to generate a larger beam diameter resulted in poorly defined dots. Therefore, we repeated the exposure process for each field seven times while subtly shifting the pattern by a few nanometers each time. As a result, we achieved an array of hexagonal patterns that eventually developed into circular shapes. The process was initiated by printing dots with 24 sides, utilizing standard, conventional techniques. Using a current of 1 nA and a step size of 5 nm, the exposure time for a square centimeter area of dots, spaced at a 208 nm pitch, was approximately 35 h. Our “dots-on-the-fly” procedure involved writing a set of seven dots: one at the standard position, a pair of dots displaced by 14 nm in the positive Y direction, and offset by ±7 nm in the X direction. An additional pair of dots was positioned 14 nm in the negative Y direction, also offset by ±7 nm in the X direction. The final two dots were aligned with the standard Y position but shifted by ±14 nm in the X direction. Figures 2(a)2(c) provide a detailed depiction of the process followed for electron beam lithography, specifically tailored for fabricating an array of circular openings with a pitch of 208 nm and a diameter of 110 nm. The initial phase of electron beam writing is shown, where the desired pitch is attained, but the diameter of the circular array is reduced to approximately 40 nm. This phase illustrates the electron beam writing with an enhanced dose, which results in a notable degradation of shape quality, as highlighted in the inset in Fig. 2(b). The final phase demonstrates the successfully optimized pattern, achieved by adjusting various parameters including a beam current of 5 nA, an aperture setting of 110, and a dose of 6.75 μC/cm2, shown in Fig. 2(c). The exposure of a square centimeter area with this arrangement required 135 min. For the final write, we used a beam current of 5 nA, 48 kV.

FIG. 2.

(a)–(c) illustrate the process development for electron beam lithography, aimed at creating an array of circular openings with a 208 nm pitch and 110 nm diameter. This process utilizes the dots-on-the-fly method: (a) depicts the initial electron beam writing, achieving the desired pitch but yielding a smaller circular array diameter (approximately 40 nm). (b) displays electron beam writing with an increased dose, leading to a significant degradation in the shape quality, as evidenced in the inset in (b). (c) presents the final, correct pattern achieved with optimized parameters, including a 5 nA beam current, an aperture setting of 110, and a dosage of 6.75 μC/cm2 (micro-Coulombs per square centimeter).

FIG. 2.

(a)–(c) illustrate the process development for electron beam lithography, aimed at creating an array of circular openings with a 208 nm pitch and 110 nm diameter. This process utilizes the dots-on-the-fly method: (a) depicts the initial electron beam writing, achieving the desired pitch but yielding a smaller circular array diameter (approximately 40 nm). (b) displays electron beam writing with an increased dose, leading to a significant degradation in the shape quality, as evidenced in the inset in (b). (c) presents the final, correct pattern achieved with optimized parameters, including a 5 nA beam current, an aperture setting of 110, and a dosage of 6.75 μC/cm2 (micro-Coulombs per square centimeter).

Close modal

In the process we have designed, the employment of a SiO2 hard mask layer, with a thickness of 400 nm, plays a pivotal role due to its chlorine etch selectivity. This property of SiO2 is not merely a beneficial attribute but is fundamentally essential for ensuring the precision and accuracy of pattern transfer, a cornerstone in our methodology. It is important to clarify the unique function of platinum (Pt) in our process. Contrary to common applications, Pt in our procedure does not serve as a hard mask in the context of chlorine etching. Rather, its use is ingeniously tailored to selectively etch SiO2. A notable aspect of this usage is that Pt retains its structural integrity throughout the process, emerging predominantly unscathed at its conclusion. Delving deeper into the nuances of etch selectivity, it becomes apparent that the SiO2 hard mask is the principal contributor to this attribute. The Pt layer, while playing a supporting role in the etching sequence, does not make a significant contribution to the overall selectivity. This distinction is crucial in understanding the material interactions at play. Moreover, our process incorporates a method of repeated pattern transfer. This is not a mere repetitive step but a carefully orchestrated part of our process that enhances the morphology of the final feature. As clearly demonstrated in the scanning electron microscopy (SEM) images provided in Fig. 3, this repetition is instrumental in refining the etched features into a more circular shape, a testament to the efficacy and precision of our methodology.

FIG. 3.

Scanning electron microscopy (SEM) depiction of the SiO2 hard mask after the platinum layer removal. The inset image shows the platinum hard mask, and circular shape formation in Pt during the selective etch.

FIG. 3.

Scanning electron microscopy (SEM) depiction of the SiO2 hard mask after the platinum layer removal. The inset image shows the platinum hard mask, and circular shape formation in Pt during the selective etch.

Close modal

The process developed in this study offers several notable benefits for creating photonic crystals. First, it allows for the consistent manufacturing of photonic crystals across a significantly large area uniformly, including 4 in. wafers. We conducted comprehensive microscopy assessments on the wafers to confirm the uniformity of the fabrication. This capability supports the scalable production of photonic crystals, catering to larger device dimensions and increased throughput.

One significant aspect of the developed process is its remarkable time efficiency, particularly in the context of e-beam lithography. The method implemented in this study has successfully reduced the e-beam lithography patterning for a 4 in. wafer to 15–16 h, which could approximately take 2750 h. This expedited fabrication time enhances productivity and facilitates rapid prototyping and efficient large-scale production of photonic crystal-based devices. In terms of etching capabilities, the process demonstrates a high aspect ratio of ≈1:30, where the radius of 68 nm and the etch depth is 2500 nm, showcasing the ability to achieve deep, vertically oriented features in the hard material GaN. This high aspect ratio etching capability is crucial for the realization of intricate photonic crystal structures, enabling precise control over the dimensions and geometry of the fabricated devices. Another significant advantage of the developed process is the ability to achieve the vertical etch of the cylindrical air holes. This characteristic is particularly desirable for electronics and optics applications that require precise control over the shape and depth of air holes within the photonic crystals. Despite the sidewalls not being perfectly parallel, the anisotropic etching achieved with this process effectively maintains the structural integrity (circular geometry) and performance required for the photonic crystals in various applications.

The double hard mask layer employed in this process exhibits exceptional endurance, rendering it highly versatile for etching and processing not only GaN but also other nitride, oxide, and carbide thin films. The robust nature of the double hard mask layer enables the fabrication of intricate photonic crystal structures while maintaining structural integrity during the etching process. This versatility expands the potential applications of the developed process to a wide range of materials and devices beyond GaN-based systems.

Moreover, the double hard mask layer demonstrates excellent resistance not only to ICP and RIE techniques but also to ion milling. This resistance ensures the stability and durability of the hard mask layer during the etching process, allowing for the precise and reliable fabrication of photonic crystal structures. In this work, the etch rate of GaN was evaluated under a range of direct current (DC) bias voltages, varying from 50 to 300 V. The results, depicted in Fig. 4, indicate an increasing trend in the etch rate with increasing voltage. To assess the temperature-dependent behavior of the etch rate, experiments were performed at both room temperature and at 270 °C. A marked increase in the etch rate was observed at the elevated temperature, with the rate being nearly three times higher at 270 °C compared to room temperature conditions. As illustrated in Fig. 5, the gallium nitride (GaN) photonic crystal is characterized through SEM. In the figure, parameter “R” corresponds to the diameter of the cylindrical holes, approximately measured at 138 nm. Similarly, parameter “a” designates the periodicity, alternatively termed the cell size, which is approximately 210 nm. In summary, the developed process showcases significant advantages for the fabrication of photonic crystals. It enables very large-area fabrication, provides high time efficiency, achieves high aspect ratio etching in hard materials like GaN, offers cylindrical air hole etching, exhibits a versatile double hard mask layer for various thin films, and demonstrates excellent resistance against etching techniques. These advantages make the process highly promising for the production of advanced photonic crystal-based devices with enhanced performance and scalability.

FIG. 4.

GaN etch rate vs DC bias voltage. The figure shows two etch rates at different temperatures; room temp. and 270 °C.

FIG. 4.

GaN etch rate vs DC bias voltage. The figure shows two etch rates at different temperatures; room temp. and 270 °C.

Close modal
FIG. 5.

SEM depiction of GaN PhC revealing uniform cylindrical air holes with a diameter of approximately 135 nm and a periodicity of 205 nm, which are etched through ICP. The inset image displays the vertical profile of GaN PhC with cylindrical air holes.

FIG. 5.

SEM depiction of GaN PhC revealing uniform cylindrical air holes with a diameter of approximately 135 nm and a periodicity of 205 nm, which are etched through ICP. The inset image displays the vertical profile of GaN PhC with cylindrical air holes.

Close modal

This paper explores the challenging task of fabricating gallium nitride (GaN) thin films with nanoscale features and high aspect ratios, used in applications such as power electronics, optoelectronics, and high-frequency devices. Traditional etching methods, such as wet chemical etching and dry etching with plasma, have been proven insufficient due to their limitations, leading researchers to investigate alternative techniques such as ion beam etching, reactive ion etching, and inductively coupled plasma etching. However, these also come with their trade-offs.

E-beam lithography, a technique often employed for its precision, struggles with the issue of slow writing speed and sensitivity to charging effects when applied to large-area fabrication. Undoped epitaxially grown GaN samples were used in this study to explore a solution. The samples underwent a series of processes, such as hard mask layer deposition, e-beam lithography, and etching steps, to produce intricate patterns.

The developed method achieved several significant outcomes, including the fabrication of photonic crystals on a large area, expedited fabrication time, a high aspect ratio of 1:30 in etching capabilities, cylindrical air hole etching, and a versatile double hard mask layer resistant to different etching techniques. This method showcases several advantages in the fabrication of photonic crystals, making it highly promising for the production of advanced devices. The study successfully devised a fabrication process for GaN thin films, tackling key challenges in the field. The new method notably enhances the efficiency and productivity of the e-beam lithography process and expands its applications to large-area fabrication. It achieves high aspect ratio etching in GaN, critical for creating intricate photonic crystal structures. The method’s ability to perform cylindrical air hole etching offers precise control over photonic crystals’ shape and depth, a desired characteristic in electronics and optics applications.

Additionally, the application of a double hard mask layer proved to be both versatile and durable in the etching of GaN thin films. This enhances the scope of the developed process, making it suitable for other challenging-to-etch nitride and carbide compounds. Given these significant advantages, the developed process is poised to advance the fabrication of photonic crystal-based devices, offering potential enhancements in performance and scalability. The outcomes of this study mark a significant leap forward in the field of GaN thin film fabrication, paving the way for advancements in power electronics, optoelectronics, and high-frequency devices.

We wish to express our profound gratitude to Dr. Charles Roques-Carmes of MIT’s Electronics Research Laboratory, Dr. Jessica Gaskin of Marshall’s Space and Flight Center, and Dr. David Ting from the Microdevice Laboratory of JPL, whose invaluable assistance, astute counsel, and experienced supervision significantly enriched our research process. Moreover, our heartfelt appreciation extends to the dedicated clean room support personnel at JPL’s Microdevice Laboratory, whose unwavering commitment to maintaining our research tools was instrumental in our work’s success. The research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration (No. 80NM0018D0004). © 2023. California Institute of Technology. Government sponsorship acknowledged.

The authors have no conflicts to disclose.

Firat Yasar: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Software (equal); Supervision (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Richard E. Muller: Investigation (equal). Arezou Khoshakhlagh: Validation (supporting). Sam A. Keo: Investigation (equal); Methodology (equal); Project administration (equal); Supervision (equal); Validation (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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