We investigate the influence of the geometry and doping level on the performance of n-type silicon nanowire field emitters on silicon pillar structures. Therefore, multiple cathodes with 50 by 50 pillar arrays (diameter: 5 μm, height: 30 μm, spacing: 50 μm) were fabricated and measured in diode configuration. In the first experiment, we compared two geometry types using the same material. Geometry 1 is black silicon, which is a highly dense surface covering a forest of tightly spaced silicon needles resulting from self-masking during a plasma etching process of single crystal silicon. Geometry 2 are silicon nanowires, which are individual spaced-out nanowires in a crownlike shape resulting from a plasma etching process of single crystal silicon. In the second experiment, we compared two different silicon doping levels [n-type (P), 1–10 and <0.005 Ω cm] for the same geometry. The best performance was achieved with lower doped silicon nanowire samples, emitting 2 mA at an extraction voltage of 1 kV. The geometry/material combination with the best performance was used to assemble an integrated electron source. These electron sources were measured in a triode configuration and reached onset voltages of about 125 V and emission currents of 2.5 mA at extraction voltages of 400 V, while achieving electron transmission rates as high as 85.0%.

Silicon field emitters, such as the black silicon (bSi) on pillar type,1,2 possess the benefit of well-established and dependable fabrication methods and can be integrated into other silicon-based devices. However, they have the drawback of generating lower emission currents when compared to typical carbon nanotube emitters.3 One feasible approach to alleviate this drawback is to optimize the number of emission tips per unit area. A new emission geometry comprised of high aspect ratio silicon nanowires (SiNWs) arranged in linear formations4 fulfills this requirement. The resulting performance increase may be explained by the reduction of field shielding between individual emission tips.5 These new geometries exhibit higher emission currents and lower onset voltages than their bSi counterparts of a comparable emission area. However, it remains unclear whether the performance improvement of these new emission structures is due to their new geometry only, or due to the different materials used for their fabrication, too. Thus, this report aims to investigate this issue by first fabricating comparable cathodes of bSi emitters and SiNW emitters to examine the effect of the geometry. In a second step, we compare two SiNW cathodes with different doping levels to study the influence of the material. A mutual problem of these types of electron sources is the alignment of the individual parts, namely, the cathode, the extraction grid, and the insulating spacer. This complex assembly frequently results in an unstable sample setup with a high risk of short circuits between the cathode and grid or a low electron transmission in a triode arrangement. This can be attributed to the distance between the grid and the cathode due to the thickness of the insulator and the loose assembly, which leads to unaligned extraction grids. Therefore, we are using the best cathode types resulting from the first two experiments to fabricate an integrated electron source. This electron source eliminates the insulating layer through substitution with a glass insulation path6 and so decreases the cathode-grid distance to nearly zero, while guaranteeing proper alignment between the two electrodes. This leads to enhanced emission performance and optimized electron transmission.

Different types of silicon chips with either SiNW structures on pillars or bSi on pillars were fabricated. The size of all chips is 8 × 8 mm2. The chips consist of a 50 × 50 pillar field emission array (FEA) of pillars with an external diameter of 5 μm and a spacing of 50 μm, resulting in an active emission area of 2.5 by 2.5 mm. To fabricate the samples, we used silicon with two doping levels: (100), n-type (phosphorus), 1–10 Ω cm (“ldSi”), and (100), n-type (phosphorus), <0.005 Ω cm (“hdSi”). All silicon wafers utilized in this study were double side polished, and had a diameter of 100 mm and a thickness of 525 μm. A spincoater Süss LabSpin8/HP8 was used for photoresist spinning. To expose the resist, we used a Süss MA/BA6 photo mask aligner. Etching was performed in an Oxford Plasmalab 80 reactive ion etcher. For the removal of the photoresist, an oxygen plasma asher TePla300PP was used.

The bSi reference samples were fabricated from hdSi. The etching mask is comprised of circles with a diameter of 5 μm. These circles serve to create pillar structures with a height of 30 μm via a photoresist mask through the process of anisotropic plasma etching. Following this step, bSi is structured by reactive ion etching according to Refs. 1 and 7 [Fig. 1(a)]. For the SiNW samples, the etching mask comprises ring-shaped features with a circular inner boundary and an outer boundary in the shape of a twelve-pointed star [Fig. 1(c)]. With this geometry, two types of samples from hdSi and from ldSi were fabricated. A layer of photoresist (AZ5214) was initially spun onto the sample. The layer was then exposed in contact exposure mode, creating a slight gap between the photoresist and the mask during exposure. The exposure dose was maintained at approximately 20% above the advised level for this resist. The gap allows light to diffract beneath the structures on the mask and partially expose the thinner parts of the mask features. Subsequently, the exposed photoresist was developed [Fig. 2(a)], leading to unevenly shaped resist rings with width fluctuations due to the mask and uneven thickness caused by the light source’s diffraction during exposure [Fig. 1(d)]. The next step involved the anisotropic etching of these rings using a cyclic plasma etching technique. The etching process is not 100% selective between silicon and resist; hence, both materials are attacked simultaneously. Due to the lesser volume of resist in the thinner and narrower sections of the rings, these sections are removed before the wider and thicker areas. This leads to the etching of a ring first, creating a tube structure [Fig. 2(b)]. When the photoresist ring breaks up due to the etching selectivity, a twelve-point crown results because material removal initiates in the opened-up sections [Fig. 2(c)], while the tube is still growing in height. The etching proceeds and results in the shrinking of the remaining resist patches, automatically sharpening the points of the crown [Fig. 2(d)]. This process yields the tubular shaped emitter structures, with the aforementioned high aspect ratio SiNWs on top. Finally, the photoresist residues are removed by oxygen plasma ashing [Fig. 1(b)].

FIG. 1.

Scanning electron microscope (SEM) images of the cathode structures. (a) bSi reference structure. (b) New geometry with tubular emission structures and SiNW emitters on top. (c) Drawing of the mask features used to structure the SiNW emitters. (d) Ring consisting of photoresist structured for the SiNW geometry. One can see the irregular height and width.

FIG. 1.

Scanning electron microscope (SEM) images of the cathode structures. (a) bSi reference structure. (b) New geometry with tubular emission structures and SiNW emitters on top. (c) Drawing of the mask features used to structure the SiNW emitters. (d) Ring consisting of photoresist structured for the SiNW geometry. One can see the irregular height and width.

Close modal
FIG. 2.

Fabrication steps of the SiNW samples. Depicted is a cut through the center of one of the radially symmetric emission pillars. The darker shade of gray is the cut silicon. The lighter gray is the interior of the hollow cylinder, visible due to the cut through the pillar. (a) Structured photoresist. (b) and (c) Partially etched emitter. (d) Finished emitter with photoresist residues removed.

FIG. 2.

Fabrication steps of the SiNW samples. Depicted is a cut through the center of one of the radially symmetric emission pillars. The darker shade of gray is the cut silicon. The lighter gray is the interior of the hollow cylinder, visible due to the cut through the pillar. (a) Structured photoresist. (b) and (c) Partially etched emitter. (d) Finished emitter with photoresist residues removed.

Close modal

To apply the high field needed for the field emission of electrons, a second electrode is used, which is placed geometrically close to the cathode in order to reduce the extraction voltage needed. The extraction electrode can be realized using different techniques to achieve a uniform electric field, enhanced performance, and transmission. Silicon nitride membranes can be used to obtain fine meshed extraction grids.7 Other researchers8,9 chose to integrate the extraction electrode into the cathode to obtain a similar outcome. In this instance, extraction grids were fabricated geometrically matching to the cathodes from hdSi with grid openings of 30 μm and a grid spacing of 50 μm. The grids were manufactured by using a silicon dioxide hard mask on the front side.

This was achieved by creating a photoresist mask on a silicon oxide coated wafer (700 nm thermal), followed by plasma etching [Fig. 3(a)]. The grid apertures were structured using an anisotropic plasma etching process [Fig. 3(b)]. The wafer’s front side was protected by thermal oxidation after photoresist removal. After creating a hard-mask on the back side of the wafer, the bulk silicon was chemically removed with a 20% tetramethylammonium-hydroxide solution at 85 °C until the grid structures were exposed [Fig. 3(c)]. Finally, hydrofluoric acid was used to remove the remaining silicon dioxide [Fig. 3(d)].

FIG. 3.

Fabrication steps of the extraction grids. (a) Opened silicon oxide hard-mask. (b) Grid openings obtained by dry etching. (c) Backside hard-mask is structured, and the grid opened wet chemically. (d) Silicon oxide is removed. The extraction grid is ready for use.

FIG. 3.

Fabrication steps of the extraction grids. (a) Opened silicon oxide hard-mask. (b) Grid openings obtained by dry etching. (c) Backside hard-mask is structured, and the grid opened wet chemically. (d) Silicon oxide is removed. The extraction grid is ready for use.

Close modal

The cathodes were initially evaluated in a diode setup (Fig. 4). Three types of samples were characterized. One type was the bSi reference made from hdSi (“hdbSi”), and the other two types were SiNW emitters: one made from the same material (“hdNW”) and the other type from ldSi (“ldNW”).

FIG. 4.

(a) Schematic of the setup used for characterizing the samples. The cathode is connected via a 10 kΩ resistor through the cathode voltage source (Vc) and the cathode current meter (Ic) to the ground. The grid is mounted on top of the cathode with a 50 μm mica spacer and is also connected to the ground. IV-plots of the cathode current (Ic) as a function of the cathode voltage (Vc), which contain several series of measurements taken up to different maximum voltages (measuring sequence: 400 V-run, 700 V-run, 1 kV-run). (b) depicts the black silicon reference (hdbSi), (c) high doped nanowire (hdNW), and (d) the low doped nanowire (ldNW). The baseline of the 1 kV-run is higher because the emission current exceeded the default fixed measurement range used, and, therefore, the next higher range was set.

FIG. 4.

(a) Schematic of the setup used for characterizing the samples. The cathode is connected via a 10 kΩ resistor through the cathode voltage source (Vc) and the cathode current meter (Ic) to the ground. The grid is mounted on top of the cathode with a 50 μm mica spacer and is also connected to the ground. IV-plots of the cathode current (Ic) as a function of the cathode voltage (Vc), which contain several series of measurements taken up to different maximum voltages (measuring sequence: 400 V-run, 700 V-run, 1 kV-run). (b) depicts the black silicon reference (hdbSi), (c) high doped nanowire (hdNW), and (d) the low doped nanowire (ldNW). The baseline of the 1 kV-run is higher because the emission current exceeded the default fixed measurement range used, and, therefore, the next higher range was set.

Close modal

The specimens were prepared by attaching an extraction grid with a 50 μm mica spacer to the cathode. They were then introduced into a vacuum chamber at a pressure of 10−9 mbar. The extraction grid was maintained at 0 V, while a FUG MCP140 applied a negative voltage to the cathode. The cathode current was determined via a Keithley 6517B [Fig. 4(a)]. The procedures for measurements were as follows: First, a check for short circuits between emitter and grid was performed. If this check was passed, the extraction voltage was ramped up to 400 V and held for an hour to activate (condition/burn in) the tips.6 Following this, three IV-characteristics were measured in 5 V steps up to 400 V (up and down). Prior to averaging all six datapoints (three datapoints for up-sweeps and three datapoints for down-sweeps) for each extraction voltage applied, the voltage drop across the resistor was compensated. This process was repeated for extraction potentials of 700 V and 1 kV.

The onset voltage is determined in Secs. III BIV C by the intersection of the average level of the background noise in the current measurement and the extrapolation of the approximately linear portion of the emission curve. The hdbSi type showed no activation during the 400 V run [Fig. 4(b)—red trace (400V-RUN)], while the hdNW was already operational, generating a maximum current of 110 nA with an onset voltage of 325 V [Fig. 4(c)—red trace (400V-RUN)]. The ldNW type also became operational during the 400 V test, emitting a maximum current of 80 nA with an onset voltage of 325 V [Fig. 4(d)—red trace (400V-RUN)]. All types were operational for the 700 V run. HdbSi reached 25 μA at an onset voltage of 400 V [Fig. 4(b)—green trace (700V-RUN)], while the hdNW cathode reached 30 μA, with its onset voltage increasing to 410 V [Fig. 4(c)—green trace (700V-RUN)]. The ldNW specimen exhibited a maximum current of 160 μA, while reducing its onset voltage to 250 V [Fig. 4(d)—green trace (700V-RUN)]. At the 1 kV run, the onset voltage of the reference increased to 550 V, while the current remained unchanged [Fig. 4(b)—blue trace (1000V-RUN)]. Moreover, the hdNW sample displayed an increase in the onset voltage to 550 V, accompanied by a rise in the maximum emission current to 50 μA [Fig. 4(c)—blue trace (1000V-RUN)]. The ldNW specimen yielded a maximum emission current of 2 mA, with an onset at 325 V [Fig. 4(d)—blue trace (1000V-RUN)]. Both types using the SiNW geometry are slightly emitting already at 400 V, unlike hdbSi.

This implies that the electric field at the emission tips for SiNW samples must be slightly higher for a given extraction voltage. Consequently, it is assumed that the field enhancement is slightly higher for these samples. Furthermore, both geometries have a comparable macrogeometry; i.e., the pillars in both cases share similar height and diameter. Hence, to understand these results, the nanostructures at the top of the pillars must be considered. The bSi boasts a dense arrangement of needles, whereas in the SiNW samples, the emission tips are sparser and more widely dispersed [Figs. 1(a) and 1(b)]. McClain et al.10 and Biswas and Rudra11 have reported on the impact of field shielding between the emission tips of the FEA. If the tips are packed too closely together, they will shield each other from the electric field. This reduces the magnitude of the electric field at each tip’s apex and increases both the extraction voltage required for activation and the onset voltage of the activated FEAs. In both samples made from hdSi, the onset voltage increases with each run. An increase in the onset voltage can be attributed to the fact that the emission tips become dull due to degradation, resulting in a decrease in their field enhancement. Another reason could be that the emission tips, or entire pillars of the FEA, are destroyed, changing the number of available emission spots. Postmeasurement scanning electron microscope (SEM) analysis showed that for the hdSi samples, entire pillars are indeed melted and destroyed [Fig. 5(a)]. However, this appears not to be the case for the ldSi samples [Fig. 5(b)]. Since Fig. 5(a) suggests a thermal cause of destruction for high doped material cathodes, two thermal effects must be considered for field emission: first, Joule heating, due to the ohmic resistance of the material, and second, the Nottingham effect at the emission sites. Thus, the following sequence of events may explain our findings. Increasing the extraction voltage leads to an increase in the electric field at the emission tips. The emission tips with the highest field enhancement start to emit first, resulting in the majority of the emission current being carried by a few emitters, which are the sharpest emission tips of the whole array. Baturin and Baryshev showed this phenomenon using a visualizing measurement setup.12 Due to the material’s high doping level and, therefore, low ohmic resistance, there is a minimal voltage drop for a given emission current, enabling the emission current of the tips to freely rise with the field, as per the Fowler–Nordheim equation. However, the small but present voltage drop due to the resistance of the material in combination with the Nottingham effect, as described by Paulini et al.13 and Charbonnier et al.,14 leads to a heating of the tips. This process results in an increase in the number of electrons in the silicon due to the thermal generation of electron-hole pairs. Therefore, the material’s resistance decreases, allowing the emission current to increase. Subsequently, the rising emission current heats the emitters further, resulting in a divergent emission current.

FIG. 5.

SEM images after characterization. Both chips underwent an identical characterization procedure as described in Sec. III A. (a) hdNW sample after measurement. One can see the melting and destruction of pillars in different severities. (b) Nearly unchanged emission pillars of a ldNW sample after measurement.

FIG. 5.

SEM images after characterization. Both chips underwent an identical characterization procedure as described in Sec. III A. (a) hdNW sample after measurement. One can see the melting and destruction of pillars in different severities. (b) Nearly unchanged emission pillars of a ldNW sample after measurement.

Close modal

This effect of feedback can result in melting and subsequent destruction of emitters. At least it leads to significant heating of the emitters. According to Mofakhami et al.,15 the normally heating Nottingham effect can become cooling in certain situations, which they call Nottingham inversion instability. In such cases, the sign of the Nottingham effect changes beyond a specific electric field strength and material temperature (Nottingham inversion temperature). The hottest point of the emitter no longer resides at the tip but moves into the interior of the material, generating a heat flow toward the now cooler emission tip. Consequently, the material heats up drastically, due to the self-heating process, as described in Ref. 15. This likely pushes the already hot emitters beyond their melting temperature, ultimately resulting in their destruction. Therefore, because the active voltage range of the emission pillars is limited, the number of simultaneously active emitters on the array is limited by the statistical distribution of the radii of the individual emission tips. As their maximum current carrying capacity is also limited, the maximum achievable emission current of an array is also limited. So, when the sharper emitters are destroyed with increasing voltage and blunter emitters take over, the onset voltage increases from run to run. This is in agreement with our experiment [Fig. 5(a)]. However, the phenomenon was not observed in ldSi. Consequently, the ldSi array behaves more uniformly. When compared to hdSi, the voltage drop for ldSi is considerably higher for a given emission current. According to Forbes in Ref. 16, this voltage drop results in a decrease in field enhancement. Therefore, an increase in the current reduces field enhancement. Thus, the increase in the emission current with increasing extraction voltage is suppressed compared to the hdSi samples. This effect was also suggested by Cárceles.17 Even a saturation of the emission current may be achieved. Due to the more gradual increase in the emitter current, the emitters heat up more gradually, resulting in a delayed or prevented breakdown, so that the emitter tips have a wider active voltage range between their activation and destruction. The extended active voltage range of each pillar allows for the activation of more pillars simultaneously, resulting in a higher observable emission current, as also shown in Ref. 18.

For the characterization of the cathodes, the samples were assembled from three loose parts (emitter chip, mica spacer, and extraction grid). This made it challenging to ensure correct emitter-grid alignment, leading to inadequate electron transmission if measured in a triode configuration.19 Furthermore, the use of a mica spacer as an insulator leads to low reliability, often leading to short circuits between the cathode and the extraction grid. To address this issue, the extraction grid needs to be permanently attached to the cathode chip with aligned emission tips for optimized electron transfer and the mica spacer needs to be replaced with a glass insulation path.19 

To create the integrated electron source, a completed emitter wafer (Fig. 2) was anodically bonded to a Borofloat wafer. To protect the emitter pillars from contamination in subsequent processes, the front of the resulting stack was then coated with photoresist. Using laser ablation, the surrounding bulk silicon was removed from the FEAs until the underlying glass wafer was exposed. This process forms a glass isolation path between the cathode holding the emission tips and the frame encircling the chip, which functions as both a spacer and mounting surface for the extraction grid. After laser ablation, the emitter wafers underwent a process of cleaning in hydrofluoric acid to ensure the complete removal of all silicon from the isolation path. The photoresist was then removed, and the individual chips were separated. To assemble the electron sources, an extraction grid fabricated as depicted in Fig. 3 was modified by cutting one of its edges (to gain mechanical access to the cathode for electrical contact after assembly) [Fig. 6(a)]. A small amount of vacuum compatible conductive epoxy adhesive was then applied to the edge around the FEA on the emitter chip. The grid was placed on the adhesive and pressed into place. The assembly was aligned using an optical microscope until all the emission tips were positioned directly under individual grid openings [Figs. 6(a), 6(c), and 6(d)]. Subsequently, the mechanical assembly was fixed in place by thermally curing the adhesive.

FIG. 6.

(a) Explosion view of the new emission chip. The emitters are bonded to a glass carrier, which also doubles as an insulator. (b) Measurement setup for the electron source. The extraction grid is adhered to the emission chip with aligned grid openings. A tungsten needle is used as the transmission anode. The tungsten needle anode is connected through the anode voltage source (VA) to the anode current meter (IA), which is connected to the ground. The grid is connected through the grid current meter (IG) to the ground, and the cathode is connected through a 10 kΩ resistor and the cathode voltage source (Vc) to the cathode current meter (Ic) and to the ground. (c) Top view SEM image through the extraction grid onto the emitter chip. (d) Detailed top view SEM image of an emission pillar in a grid opening

FIG. 6.

(a) Explosion view of the new emission chip. The emitters are bonded to a glass carrier, which also doubles as an insulator. (b) Measurement setup for the electron source. The extraction grid is adhered to the emission chip with aligned grid openings. A tungsten needle is used as the transmission anode. The tungsten needle anode is connected through the anode voltage source (VA) to the anode current meter (IA), which is connected to the ground. The grid is connected through the grid current meter (IG) to the ground, and the cathode is connected through a 10 kΩ resistor and the cathode voltage source (Vc) to the cathode current meter (Ic) and to the ground. (c) Top view SEM image through the extraction grid onto the emitter chip. (d) Detailed top view SEM image of an emission pillar in a grid opening

Close modal

For the electron source, the diode measurement setup was extended by placing a tungsten needle approximately 10 mm above the extraction grid, which was used as the transmission anode, resulting in a triode setup [Fig. 6(b)]. A FUG HCP350 voltage source fixed the anode voltage at 500 V, Keithley 6517b measured the anode current, and Keithley 6587 measured the grid current. The measurements were performed according to the same procedure as the diode measurements, differing only in the cathode voltages used. The new electron source was characterized beginning with an extraction voltage of 50 V, which was then increased in increments of 50 up to 400 V for subsequent runs.19 

Figure 7(a) displays the IV-characteristics of the new electron source. The activation voltage was observed to decrease to 200 V, when compared to the best performing emitter in the previous study [Fig. 4(d)], where activation occurred at 400 V. This decrease is likely due to the smaller grid to cathode distance, which increases the field enhancement. At an extraction voltage of 400 V, an emission current of 2.5 mA was achieved, while the onset voltage remained at 125 V without any indication of an increase. During the activation measurement, some samples even reached 3 mA [Fig. 7(b)]. Figure 8(a) illustrates the electron transmittance measurement over a 30 min period for an extraction voltage of 250 V, and the average is 85.0%. This is about twice the electron transmission achieved in the unaligned reference measurement conducted in an identical manner using a clamped sample, which achieved 43.8% [Fig. 8(b)].

FIG. 7.

Plots of a series of measurements on one electron source up to different maximum voltages between 50 and 400 V (measuring sequence: 50 V–1 h, 50 V-run, 100 V–1 h, 100 V-run, …, 400 V–1 h, 400 V-run). (a) IV plots of the cathode current (Ic) as a function of cathode voltage (VC) for the individual runs. (b) Cathode current (IC) as a function of time for 1 h for different maximum voltages (Vmax).

FIG. 7.

Plots of a series of measurements on one electron source up to different maximum voltages between 50 and 400 V (measuring sequence: 50 V–1 h, 50 V-run, 100 V–1 h, 100 V-run, …, 400 V–1 h, 400 V-run). (a) IV plots of the cathode current (Ic) as a function of cathode voltage (VC) for the individual runs. (b) Cathode current (IC) as a function of time for 1 h for different maximum voltages (Vmax).

Close modal
FIG. 8.

(a) 30 min transmission measurement for an electron source at a cathode voltage (Vc) of 250 V and an anode voltage (VA) of 500 V. A electron transmittance of 85.0% was achieved. (b) Reverence measurement at 900 V cathode voltage (Vc) and an anode voltage (VA) of 1 kV for a clamped/unaligned HdNW sample. Here, the average electron transmittance is 43.8%.

FIG. 8.

(a) 30 min transmission measurement for an electron source at a cathode voltage (Vc) of 250 V and an anode voltage (VA) of 500 V. A electron transmittance of 85.0% was achieved. (b) Reverence measurement at 900 V cathode voltage (Vc) and an anode voltage (VA) of 1 kV for a clamped/unaligned HdNW sample. Here, the average electron transmittance is 43.8%.

Close modal

The predicted improvement by optimizing the density of the emission tips on the columns by arranging them in a geometrically optimized crown shape and, therefore, reducing the field shielding between the emission tips, was confirmed experimentally. Furthermore, we observed experimentally that reducing the dopant concentration prevents thermal destruction of the tips at high emission currents and, therefore, improves the emission characteristics. We integrated this FEA into a field emission electron source and achieved high electron transmittances of up to 85.0% and emission currents of up to 2.5 mA at extraction voltages as low as 400 V.

In further research, we will further investigate the mechanisms of the thermal destruction of the tips at high emission currents. We also intend to transfer the demonstrated integrated electron sources from single-chip fabrication to a wafer-level process, while further refining the geometry and sample configuration to further improve the emission characteristics and electron transmission.

This work was financially supported by Bayerische Forschungsstiftung under Project No. AZ-1583-23

The authors have no conflicts to disclose.

Philipp Buchner: Data curation (lead); Formal analysis (lead); Investigation (lead); Methodology (lead); Resources (lead); Software (lead); Validation (lead); Visualization (lead); Writing – original draft (lead); Writing – review & editing (lead). Matthias Hausladen: Writing – review & editing (equal). Mathias Bartl: Writing – review & editing (equal). Michael Bachmann: Writing – review & editing (supporting). Rupert Schreiner: Conceptualization (lead); Funding acquisition (lead); Project administration (lead); Resources (equal); Supervision (lead); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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