4H-SiC layer with multiple trenches in lateral double-diffused metal-oxide-semiconductor transistors for high temperature and high voltage applications

Power transistors due to their high performance are essential for intelligent power applications. Today, among different power electronic devices, lateral double-diffused metal-oxide-semiconductor field effect transistors (LDMOSFET) have been widely used in RF applications, monolithic integrated power electronic systems, and smart-power ICs.^1–6 On the other hand, silicon carbide (SiC), after silicon (Si) and gallium arsenide (GaAs) materials, is the third-generation semiconductor material. The SiC material has several advantages, such as high thermal conductivity, wide bandgap, high maximum operating temperature, and high breakdown voltage. Also, for high-frequency and high-power applications among its poly-types, 4H-SiC has gained much attraction.^7–10 The LDMOS transistors have several advantages over other power devices such as compatibility with advanced VLSI technologies, multiple output capabilities on the same chip, and also a reduction in the number of fabrication steps.^11–13 However, the major problems in LDMOS transistors are low breakdown voltage (V_BR) and high specific on-resistance $( R O n . s p)$⁠. In order to design a suitable LDMOS transistor, we must consider V_BR and $R O n . s p$⁠, but obtaining both low $R O n . s p$ and high V_BR is not possible. So, we have a trade-off between the $R O n . s p$ and the V_BR. In the last few years, to overcome this effect, various structures have been accomplished.^14–17 

Also, silicon-on-insulator (SOI) LDMOS transistors have several important advantages over traditional LDMOSFETs, such as lower parasitic capacitances, reduced latch-up, low leakage current, and high speed, and with other devices, they can be easily integrated.^18–25 However, the maximum lattice temperature of the SOI-LDMOS transistor increases due to low thermal conductivity of the buried insulator material. So, the SOI-LDMOS structure has a self-heating effect problem. In this case, to solve this problem, we can use partial SOI technology (PSOI) that has better thermal conductivity, instead of SOI technology.^26–29 

In this paper, by using a 4H-SiC layer, a novel LDMOS transistor is presented to improve the self-heating effect (SHE) and the breakdown voltage that are necessary in high-temperature and high-voltage applications. In our work, we use three key ideas: the first is inserting the p-type 4H-SiC layer in the buried oxide (BOX) to reduce the SHE; the second is locating the multiple trenches at the top of the 4H-SiC region to improve the breakdown voltage; and the third is reducing the specific on-resistance by using a Si layer with higher density than its drift region at the bottom of the drift region. So, we called the new structure as multiple trenches 4H-SiC LDMOS (MTSiC-LDMOS). The MTSiC-LDMOS is simulated by a two-dimensional ATLAS simulator.³⁰ We have shown that by optimization of multiple trenches, the maximum lattice temperature decreases and the breakdown voltage improves by flatting the electric field. The proper breakdown voltage and the self-heating effect can be mentioned as the main approaches to the MTSiC-LDMOS structure. Therefore, for high-temperature applications, the MTSiC-LDMOS device is more reliable than a conventional LDMOS (C-LDMOS).

Figure 1 presents the schematic cross-sectional view of the MTSiC-LDMOS structure. It can be seen that a 4H-SiC layer has replaced a part of the oxide layer in the BOX as a layer that benefits from good temperature reduction effects. Moreover, in the new device, the multiple trenches are located at the top of the 4H-SiC layer. As the figure shows, the L and the H are the length and the height of the trenches in the 4H-SiC layer, respectively. The p-type 4H-SiC layer that has better thermal conductivity than silicon dioxide can decrease the maximum lattice temperature in the proposed MTSiC-LDMOS. Also, these multiple trenches have been filled with an N-type silicon material. It is worth noting that the doping density of the N-type silicon is more than the drift region’s doping density. Therefore, the depletion region expands in the drift region and additional peaks are created in the electric field distribution. So, the proposed structure can effectively enhance the electric field in the drift region. So, a significant improvement in the breakdown voltage is obtained in the MTSiC-LDMOS structure.

In Table I, a list of optimum parameters for the MTSiC-LDMOS and C-LDMOS devices that are simulated in our work is presented.^14,31 Also, the fundamental parameters of 4H-SiC and silicon^32–36 are given and compared in Table II.

The 2D device simulator SILVACO is performed to have a good comparison between the MTSiC-LDMOS and the C-LDMOS transistors. In this simulation, proper models, including the analytic model, field-dependent mobility (FLDMOB) model, CCSMOB model, SHI model, LAT.Temp model, Auger recombination model, impact Selb model, and Shockley–Read–Hall (SRH) recombination, are activated. Also, to achieve more acceptable results, the interface between 4H-SiC, Si, and SiO₂ is considered at 3 × 10¹⁰ cm⁻². It is worth noting that the ATLAS two-dimensional (2D) simulator is calibrated to the experimental data.³⁷ The output characteristics of an SOI-LDMOS at V_D = 0.1 V are shown in Fig. 2. It can be concluded from the figure that the simulation results agree well with the experimental data.

We know that the applied voltage magnitude is the area underneath the electric field curve. Therefore, at a certain voltage, the heights of common peaks near the drain and source junctions are reduced by producing additional peaks in the electric field. In other words, these additional peaks in the drift region of the structure modulate surface electric field distribution such that the electric field distribution becomes more uniform and the breakdown voltage becomes more enhanced.¹² In the proposed structure, these additional peaks, which are created due to the multiple trenches that are located at the bottom of the drift region, lead to a flatter electric field. Figures 3 and 4 present the distribution of the electric field of the MTSiC-LDMOS and C-LDMOS devices in their breakdown voltages along cutline AA′ and cutline BB′, respectively. The maximum peak of the electric field happens near the junction of the drift and drain regions in the C-LDMOS transistor. However, additional peaks are created in the drift region in the MTSiC-LDMOS transistor. These additional peaks lead to an electric field distribution for the MTSiC-LDMOS that is flatter than the C-LDMOS device. As a result, a higher BV for the MTSiC-LDMOS occurs. It is important to note that to have a good comparison, we need to examine the proposed structure and the C-LDMOS device at the same drain voltage (V_DS). Therefore, in Fig. 5, the MTSiC-LDMOS and C-LDMOS devices are compared while V_DS is equal for both devices.

Also, the vertical potential distribution along the CC′ cutline is illustrated in Fig. 6. It is clear that the BV of the MTSiC-LDMOS and C-LDMOS devices is 65 and 36 V, respectively.

As already discussed in the Introduction, the lattice temperature of the C-LDMOS transistor increases because the BOX material is silicon dioxide. Due to the low thermal conductivity of the buried SiO₂ material, the lattice temperature of the C-LDMOS transistor increases with drain voltage. However, for the proposed MTSiC-LDMOS device to reduce the self-heating effect, we use the 4H-SiC layer that has better thermal conductivity than silicon dioxide. By using the 4H-SiC layer at the BOX of the MTSiC-LDMOS structure, a lower lattice temperature compared with the C-LDMOS device is achieved. The maximum lattice temperature against the drain voltage at V_D= 20 V and V_G= 8 V for both devices is depicted in Fig. 7. When the drain voltage bias increases, the lattice temperature and, then, the self-heating effect for both devices increase, but a lower lattice temperature in the MTSiC-LDMOS will achieve this. The maximum lattice temperatures in the MTSiC-LDMOS and C-LDMOS transistors at V_G= 8 V and V_D= 20 V are 363 and 310 K, respectively.

Other main parameters in power transistors are the drain current and the $R O n . s p$⁠, which are mentioned earlier. Figure 8 shows the drain current at V_G= 8 V and V_D= 20 V for the MTSiC-LDMOS and C-LDMOS structures. The proposed MTSiC-LDMOS device has a higher drain current than the C-LDMOS structure. Also, the specific on-resistances as a function of N-drift length for the MTSiC-LDMOS and C-LDMOS devices are shown in Fig. 9. It is clear from Figs. 8 and 9 that the MTSiC-LDMOS has a smaller $R O n . s p$⁠. This is because of the multiple trenches in the proposed MTSiC-LDMOS device that have higher doping density than its drift region.

Now, we present design considerations of the proposed MTSiC-LDMOS device to improve the specific on-resistances, the breakdown voltage, and the lattice temperature. As the doping density of the multiple trenches increases, the $R O n . s p$ decreases. However, on the other hand, the breakdown voltage will decrease. So, we need to find an optimal amount of doping density for the multiple trenches, where the BV will be the highest and the $R O n . s p$ will be the lowest. To find the best optimum value of the trench doping density, Fig. 10 is drawn where the BV and $R O n . s p$ are plotted in this figure. The gate voltage is considered 0 V to obtain the BV. Also, the $R O n . s p$ is obtained in the drain voltage of 1 V and the gate voltage of 10 V. The best value of the doping density as the figure shows is 10¹⁷ cm⁻³.

As mentioned earlier, our proposed structure is suitable for applications where the temperature is of great importance. On the other hand, in the proposed MTSiC-LDMOS structure, we have to optimize the multiple trenches to obtain suitable results. For this purpose, the maximum lattice temperature for the MTSiC-LDMOS structure for different lengths of multiple trenches is drawn in Fig. 11. As can be seen from the figure, the maximum lattice temperature decreases as the length of multiple trenches increases while the breakdown voltage increases. So, we seek the optimum value where the breakdown voltage is the highest and the lattice temperature is the lowest. Therefore, according to Fig. 11, the best length for the multiple trenches is 0.5 μm, in which the maximum lattice temperature and the breakdown voltage are 310 K and 65 V, respectively.

After optimizing the value of the length of multiple trenches, we must also check the value of the height of multiple trenches. So, the breakdown voltage and the maximum lattice temperature for the MTSiC-LDMOS structure are plotted for different heights of multiple trenches in Fig. 12. As indicated in the figure, for a specific height value of the multiple trenches, there is a maximum lattice temperature and a breakdown voltage for the proposed MTSiC-LDMOS structure. As can be seen from the figure, the best height value to have a simultaneous highest breakdown voltage and the lowest temperature is 0.1 μm. It is worth noting that when the height of trenches is 0.1 μm, the electric field distribution for the MTSiC-LDMOS is flatter than the other cases. As a result, a maximum BV for the MTSiC-LDMOS for H = 0.1 μm occurs. Also, we set the gate voltage to 0 V to obtain the breakdown voltage in Figs. 11 and 12 and to obtain the maximum lattice temperature, we set the gate and the drain voltages to 8 and 20 V, respectively.

In conclusion, a comparison between the proposed MTSiC-LDMOS, C-LDMOS, the proposed MTSiC-LDMOS with 6H-SiC material instead of 4H-SiC material (6H-MTSiC-LDMOS), and other devices is mentioned in Table III. It is worth noting that in addition to the advantages of the proposed structure, the use of 4H-SiC material in the proposed MTSiC-LDMOS also has some problems such as making the part more complicated compared to the C-LDMOS.

We presented a novel LDMOS transistor for improving the self-heating effect and the breakdown voltage in this paper. A 4H-SiC layer was replaced in a part of the buried oxide region (BOX). Moreover, the top of the 4H-SiC layer has multiple trenches that have been filled with an N-type silicon material. The proposed device was called multiple trenches 4H-SiC LDMOS (MTSiC-LDMOS). By using the multiple trenches 4H-SiC layer at the proposed device, we saw an enhancement in the breakdown voltage and a reduction in the maximum lattice temperature. Also, the results of the MTSiC-LDMOS structure that is extracted from the two-dimensional ATLAS simulator showed an improvement in the current flow and the specific on-resistance. Therefore, for high breakdown voltage and high temperature, the MTSiC-LDMOS device is more reliable than a conventional LDMOS (C-LDMOS) device.

The authors received no financial support for the research, authorship, and/or publication of this article.

The authors have no conflicts to disclose.

Amir Sohrabi-Movahed: Conceptualization (lead); Software (equal); Writing – original draft (lead). Ali Asghar Orouji: Methodology (equal); Supervision (lead); Writing – review & editing (equal).