Barrier/seed system for electroless metallization on complex surfaces using (aminomethylaminoethyl)phenethyltrimethoxysilane self-assembled films

Modern electronics operate at high frequencies. Inductance effects push the current in such circuits to the surfaces or edges of the conductors. This necessitates the seed layers for electrodeposited conductors to have low electrical loss, as they are inherently at the edge. The electrical properties of the first layer of metal, the seed layer, are not well studied, despite their importance at high frequency operations. Significant efforts in self-assembled monolayer (SAM)-based seed layers¹ include deposition on TaN,^2,3 selective area deposition involving Co particles,⁴ sprayed-on or plasma-grown Ag particles,^5,6 and no seeds at all.⁷ Three-dimensional (3D) integration and packaging has gained significant interest in recent years for both complementary metal-oxide semiconductor (CMOS) and radio frequency (RF) modular applications.⁸ Patterning of the seed layer is also of interest^9–12 as is inverse patterning¹³ and direct bonding of copper pads through an electroless Cu layer.¹⁴ Of particular interest in the common “via-last” packaging design that Gary McGuire, the honoree of this special issue, worked on for many years, is the signal performance of through-silicon vias (TSVs). The surface of the TSVs is the seed/initial metal layer and hence must be low-loss. Within the next 3–5 years,¹⁵ TSV diameters ranging from 0.8 to 1.5 μm with aspect ratios ranging between 10:1 and 20:1 and pitch lengths between 1 and 4 μm are expected, meaning that the first metal layer makes up a larger portion of the via volume. At high frequencies (HF > 0.4 GHz), signal attenuation occurs due to inductive-capacitive (LC) delay. The conduction area is limited to the penetration depth times the via perimeter. Given a fixed perimeter size, permeability is reduced and skin depth increased by materials choice (Cu rather than Ni) and by reducing resistivity of the outermost layer (the first metal). Here, we address the optimization of the resistivity of this first metal layer, while maintaining good morphology and adhesion. We use a SAM layer to attach a catalyst to an arbitrarily shaped surface.¹⁶ Since rough, wavy, scalloped surfaces are easy to fabricate compared to smooth, tapered holes,^17–19 especially at high (>10) aspect ratios, we term our technique “smart” seed layers for via formation in easy-to-fabricate holes. The use of (aminomethylaminoethyl)phenethyltrimethoxysilane (PEDA) as the SAM, with a catalyst for electroless deposition of Cu rather than Ni,²⁰ and the optimization of the quality of this first Cu layer, are contributions of this work.

Barrier layers^21–23 are needed to minimize diffusion between the conductor and substrate. We propose the use of (aminomethylaminoethyl)phenethyltrimethoxysilane (PEDA), which is aromatic so should be an effective barrier layer.²³ As a SAM layer with amine termination, it provides a conformal, catalytic surface for electroless deposition. It also can be selectively patterned with deep UV lithography. Finally, it can be processed with low-temperature (<200 C) techniques, which is important in a via-last application. Electroless deposition,^24–27 where the copper layer plates from solution onto a catalytically activated surface, has emerged as a viable low temperature alternative to existing TSV seed layer deposition techniques. In response, many studies^28–32 have attempted to find compatible means of electroless barrier layer deposition; however, this particular process has its drawbacks. Existing physical-deposition methods catalyze the underlying insulation layer, which can generate impurity diffusion into the insulation layer and silicon. Given the breadth of processing challenges, we have chosen the PEDA-catalyst-electroless deposited Cu system that has the advantages described above. We find that the quality of the copper layer is strongly influenced by the PEDA and catalyst processes as well as the electroless deposition itself and show its optimization here.

In this paper, we aim to quantify the process conditions that produce high-quality electroless copper seed layers upon the PEDA barrier layer, since this outermost layer controls high frequency performance. We show that it is possible to make a barrier/seed layer that is capable of rapid deposition of high-quality copper, all while maintaining good barrier layer characteristics. This work reviews the parts of this problem already addressed and focuses on the remaining issues to be solved, which relate primarily to correlating the quality of the catalyzed SAM layer to the subsequent quality of the deposited copper seed layer. We find through skin depth calculations that optimization of the seed layer is critical above several GHz. Briefly, we propose a “smart seed and barrier” to work with a simple (easily fabricated) via hole, as opposed to a simply deposited seed layer in via hole that must be fabricated with tight parameter controls for uniform angle, smooth walls required by the simple (physically deposited) seed.

Our copper metallization technique is based on an approach described for nickel deposition.^1,33–35 To characterize the metallization process, we use the sessile drop method^36–42 to determine optimal PEDA deposition time. Once the copper layers are deposited, we determine the copper quality by measuring the copper thickness and film resistivity as a function of catalyst and copper bath deposition time. De-ionized water with >18 MΩ resistivity was used throughout the experiment. PEDA used in the experiment was obtained from Gelest, Inc. All solvents were obtained from Fisher Scientific. Disodium tetrachloride palladate, Na₂PdCl₄⋅3H₂O, was obtained from Aldrich Chemical Company. All other acids were obtained from Fisher Scientific. The copper bath is a commercially available solution obtained from Transene, Inc. The PEDA samples were prepared on native oxide Si wafers [n-type (100), Wafer World]. Two sets of six 1 in. square silicon samples were cleaned in a piranha etch consisting of a (1:1 v/v) H₂SO₄/H₂O₂ solution for 1 h, rinsed in DI water, then passivated in a 3% HF solution for 7 min. After another DI rinse, the first set of samples was immersed in a 1% PEDA solution for 15 min, then submerged in a colloidal palladium catalyst dispersion for an additional 15 min, following the recipe of Brandow et al.⁴³ Their recipe called for a filtering of the final solution in a 0.22 μm Teflon filter; in lieu of the filter, we used a Stokes' law analysis to estimate the time for particles of this size or greater to float down to the bottom of our container, keeping it refrigerated at 8 °C to hasten excess growth of particles of the desired size. The samples were then rinsed in isopropanol for 2 min, submerged in the copper solution at 40 °C, and removed in sequence after 15, 30, 60, 120, 240, and 480 s of deposition time. The second set of samples was submerged in PEDA for 15 min, then dipped in a separate Pd solution, removed in sequence after 1, 2, 4, 8, 15, and 30 min, rinsed in isopropanol for 2  min, and finally submerged in a separate copper bath for 2 min. The contact angles of the PEDA films were measured using a custom designed sessile drop system. The thicknesses of the copper films were measured using a Dektak profilometer and resistivities measured with a Keithley four-point probe. AFM measurements utilized a Digital Instruments Nanoscope III.

Surface functionalization of PEDA requires a hydrogen-passivated surface prior to deposition. If the substrate is not properly hydrolyzed, the quality of PEDA deposition will be compromised. We, therefore, establish the optimal PEDA deposition time by measuring the sessile drop contact angle as a function of PEDA deposition time at a fixed passivation time of 7 min, as stated in Sec. II. Figure 1 shows contact angle measurements after PEDA deposition as a function of deposition time. According to prior studies,³⁹ the contact angle for a high-quality PEDA layer is approximately 52°–55°. Figure 1 shows that after an initial increase in contact angle during the first 15 min of deposition, the contact angle eventually settles into the 52°–55° range, suggesting that the optimal PEDA deposition time is between 15 and 30 min. This provides a high-quality single layer with minimal possibility of multiple layer growth.

The next step in the deposition process is PEDA catalysis and its role in the quality of the copper seed layer. The ideal PD2 conditions should allow for the deposition of a reproducibly thin (∼100 Å) seed layer, whose sheet resistivity, ρ_s, should approach that of bulk copper, approximately 0.0168 μΩ m.⁴⁴ To determine the dependence of copper thickness and resistivity on growth variables, we establish a reference point in an independent variable space that includes four degrees of freedom: PEDA deposition time, PD2 catalysis deposition time, copper bath temperature, and copper bath deposition time. As described above, the optimal PEDA deposition time is ∼15 min, eliminating one degree of freedom. The bath temperature is kept constant at 40 °C, per the deposition instructions of the Transene solution, thus eliminating another degree of freedom. This leaves two parameters, PD2 and copper bath deposition time, to adjust, while noting the PD2 and copper film thickness and optimizing the resistivity and film mechanical properties: morphology and substrate adherence. After determining the thickness growth rate, the resistivity is easily quantified and we optimize it by independently varying the parameters to get “line-cuts” of the surface of the resistivity as a function of these two parameters. These line-cuts cross at a reference point, which we find is not far from the optimal conditions. The growth conditions of our chosen reference point are 15 min of PEDA growth, 4–8 min of PD2 growth, and 2–4 min of copper growth. For catalysis, there is an ideal balance between both the particle size and palladium ion concentration collected by each amine end group of PEDA. Figure 2 shows in the top row a schematic of the PD2 development in relation to its resultant copper film growth quality in the bottom row. The proper catalyst layer is a uniformly sized, tightly distributed Pd catalyst layer that yields high-quality smooth films that adhere well to the substrate, as shown in Figs. 2(c) and 2(d). At one processing extreme, too short a PD2 deposition time results in too few Pd ions collected per amine group, resulting in broken, non-uniform copper layers. These layers do not adhere well to the PEDA and tend to crack, bubble, and peel, as shown in Figs. 2(a) and 2(b). At the other processing extreme, too long a PD2 deposition creates Pd particles ions of varying size per amine group, resulting in a rough copper layer, sporadically attached to the underlying PEDA layer, that adheres poorly to the silicon substrate, as shown in Figs. 2(e) and 2(f).

The film thickness and resistivity data as a function of PD2 and copper deposition time is shown in Figs. 3(a) and 6(b). For a fixed PD2 deposition time of 15 min, there is a linear dependence of copper thickness to copper bath deposition time, ranging from 0.4 nm at 30 s of deposition time to 600 nm at 8 min of deposition time, corresponding to a deposition rate of approximately 0.184 mil/h. This is close to the nominal deposition rate of 0.2 mil/h. For a fixed copper deposition time of 2 min, the measured copper thickness is initially large at short PD2 deposition times (e.g., 345 nm at 1 min of PD2 deposition) due to direct Cu-PEDA bonding. As PD2 deposition time increases however, copper thickness decreases due to direct Cu-PD2 bonding, reaching a minimum of 18.2 nm at 15 min of PD2 deposition before rising to a value of 228 nm at 30 min as the PD2 particle size distribution increases.

Copper resistivity also reflects film quality changes with Pd and Cu growth times. For the copper bath time variation, short bath times (i.e., <60 s) yield resistivities approaching that of bulk copper. The resistivity spikes up to 6.92 μΩ m at the 1 min mark, as the relatively thick (60 nm) copper layer grown atop the Cu-PEDA bond begins to relieve stress and form defects. As time progresses, the resistivity then drops to a minimum of 0.0415 μΩ m at 4 min, still an order of magnitude higher than that of sheet copper resistivity, due to the growth inconsistencies of the underlying 15 min PD2 layer. The resistivity dependence on PD2 deposition time surface trends in a similar fashion, with a value of 0.5 μΩ m at 1 min of PD2 deposition, due to Cu-PEDA bonding and other film defects. Bulk copper resistivity is approached near 4 min, reaching a minimum of 0.009 36 μΩ m at 8 min. The resistivity rises for longer catalyst deposition times. This dependence on growth reflects the stages of PD2 development outlined in Fig. 3.

Comparisons of the data in Fig. 3 suggest that the optimal growth conditions are 15 min of PEDA deposition, 4–8 min of PD2 deposition, and 2–4 min of Cu deposition at 40 °C, since the resistivity data for both parameter variations trend toward the value of bulk copper sheet resistivity. The four minutes of PD2 deposition differs from the reference value of 15 min, as it gives an improvement. The copper deposition time of four minutes rather than two is less significant. The broad minimum against variation of each parameter suggests that these values are robust, and slightly better results would be attained near the minimum of these curves at optimal growth conditions. An important point is that a resistivity near the bulk value is reached at thicknesses below 300 nm. As stated before, lower loss at RF is attained when the transition to high-quality copper is fast. The size and distribution of the Pd catalyst used here in our Cu_seed/PEDA system seems to outperform the APTMS and APTES systems used in other work,^45–51 whose subsequent Cu layer resistivity is on average 2–3 times higher than the bulk Cu resistivity. Our system also incorporates the benzene ring within the PEDA molecule, lacking in the aliphatic SAMs used by the other groups. The aromatic ring has been shown²³ to improve both thermal stability and reduce diffusion (likely due to an increase in the layer density at the ring), hence improving its action as a barrier layer.

Atomic force microscopy images of the optimal process at various stages can be used to verify the process and provide accurate measures of the catalyst and Cu grain sizes. The bare, clean Si surface and PEDA layer are flat to within a few nm, so are not shown. The catalyst and copper layers are shown in Figs. 4(a) and 4(b). The vertical range of the catalyst image over the ten-micron squared region is only 20 nm and has the appearance of a few catalyst particles sitting on top of a layer of particles. This suggests a catalyst size in the 10–20 nm range as desired and anticipated. Such a size is further supported by the line cut from the white line in the figure, shown in Fig. 4(c), which shows features of similar width a little larger than the 10–20 nm on top of a background with regular oscillations, suggesting the primary layer. The reproducible shapes point to AFM tip effects artificially broadening the imaged particles. It is a pyramidal-shaped tip, so the particles on top are broadened more than those in the layer. The horizontal measured dimensions are thus consistent with the vertical dimensions. The image of the final copper electroplated surface is smaller, two microns squared, but is also extremely smooth, within 10 nm over this area. This indicates a good coverage and indicates that the occasional “catalyst particle on top of the layer” does not roughen the copper surface. These data are from optimal growth conditions.

We organize the discussion by reiterating the important capabilities for a “smart” seed layer, and both review past efforts while illustrating how our results augment them.

In our work, we ultimately seek to find a single material that facilitates both seed layer functionality and selective patterning. Photolithography using SAMs has been extensively studied and characterized.^33–43,52 The main advantages of SAM masks over organic photoresists are twofold. First, by careful selection of the binding and alkyl groups, such SAM layers can be selectively patterned under DUV radiation for high resolution metallization etch layers.³⁶ Deep UV light exposure cleaves the SAM molecule near the attachment point, removing the functional portions of the SAM later, so that metal deposition can be selectively patterned.³⁶ Second, by careful selection and catalysis of the ligating end group of the SAM layer, numerous types of metallic layers, including copper, nickel, and cobalt, have been grown atop the patterned layers.^{36–38,40–43} For our purposes, the ideal SAM layer has three characteristics: (1) a binding group that bonds to a silicon/silica surface, (2) an alkyl group that selectively absorbs DUV radiation, (3) a ligating end group that allows for electroless metallization. Prior research has focused on the use of organosilanes, specifically trimethoxysilanes, as the binding group. The methoxysilane groups react with hydroxyl groups to form siloxane bonds and liberates methanol as by-products.^36–43 These are ideal reactions for silicon, which creates high-quality oxides for use for hydroxyl groups.

The selection of the alkyl group is guided by two principles: (1) complete DUV absorbance and alkylamine photocleavage and (2) DUV dosages and photospeeds that prevent photoablation, as opposed to photocleavage, of the underlying binding group or substrate. Initial studies^36–42 identified organosilanes with aromatic functional groups as effective SAM layers for DUV photocleavage. The phenyl groups are highly absorbing at DUV wavelengths, including the 193 and 248 nm lines. Studies with SAM layers aromatic groups, including phenyltrichlorosilane (PTCS),^{35,36,42,49–51} 2-(trimethoxysilyl)ethyl-2-pyridine (PYR),^{37,38,40,43,44} (aminomethylaminoethyl)phenethyltrimethoxysilane (PEDA),^{35,39–41,43} and chloromethylphenyltrichlorosilane (CMPTS)^35,52 have shown effective photocleavage of their respective aromatic groups at the Si–C bond. Our ideal SAM layer should thus possess a very short photospeed with a large quantum yield.

The dosage characteristics of the studied aromatic SAM layer are shown in Table I. Exposure doses are inversely proportional to the absorptivity of the chromophore in the film as well as the photoprocess quantum yield.^41,42 On one end of the dosage scale, PYR films, with a molar absorptivity coefficient of 1.2 × 10⁴ l/mol cm at 193 nm, require a dose of 4.5 J/cm² for total Si-C photocleavage⁴¹ which is too large for high resolution lithography. On the opposite end of the dosage scale, CMPTS films (ε_193 nm = 5 × 10⁴ l/mol cm) have exhibited photocleavage at doses <50 mJ/cm² at 193 nm. However, such films require an extra step by which the ligating end groups are grafted onto the remaining patterned SAM layer.³⁵ Both PEDA and PTCS films possess comparable molar absorptivity coefficients at 193 nm (ε₁₉₃ =4.7 × 10⁴ l/mol cm vs 5 × 10⁴ l/mol cm, respectively), resulting in comparable photocleavage dosages of 400 mJ/cm². However, since PTCS does not include the extra ligating end group, it does not meet the necessary characteristics for a suitable SAM mask layer, leaving PEDA as the best SAM layer choice for both patterning and etch layer protection due to its DUV absorbing aromatic alkyl group and its diamine ligating end group.⁴¹ 

Since prior groups have demonstrated the high temperature resistance⁴⁷ and patterning selectivity^36,43 of PEDA barrier layers for use in Cu metallization, we aim in this work to correlate the catalytic behavior of the activated PEDA layers to the eventual as-deposited quality of the copper seed layer. Surface catalysis is accomplished by treating the substrate with a colloidal suspension of Pd and Sn species. The colloidal particles consist of a Pd metallic core, 5–20 nm in diameter, surrounded by an Sn-rich layer. The central core is comprised of a low-valence, Pd rich intermetallic species, which acts as the actual catalyst in the initial reduction process leading to plating. Prior research³⁸ has found that the Pd/Sn catalyst adheres sufficiently to enable electroless metallization of surfaces modified with terminal olefin, amine, thiol, hydrocarbon, heterocyclic, phosphocholine, and other functional groups. The Pd/Sn catalyst, however, does not adhere to surfaces with high levels of free Si-OH groups. The diamine group found in PEDA is thus suitable for Pd/Sn catalysis. The critical characteristics of a successful catalysis layer are small particle size, small particle size distribution, and complete particle coverage of the SAM layer. If the particle size (∼10–20 nm) or distribution (± 20 nm) is too large, the grain size of the resulting EL Cu will be uneven, as larger catalyst particles form larger Cu grains, and minimize the contributions of smaller particles. Grain size considerations become even more critical for TSV seed layers as the aspect ratio of the catalyzed surfaces increases. Initial TSV SAM barrier/seed studies^32,45–50 catalyzed their SAM layers using a gold based colloidial suspension, due to the inability to control the particle size distribution of traditional Pd/Sn based catalysis. Although successful in creating monodisperse suspensions, Au diffusivity into silicon is undesirable. Several groups^38,40,43 have previously addressed catalysis issues in EL nickel metallization using careful Pd particle size control and Sn layer elimination, and whose strategies are employed in our EL copper metallization. Our catalysis method, as described by Asher et al.,⁴³ creates an initial rapid nucleation of Pd particles in solution, which is subsequently neutralized to sufficiently control growth. Similarly, both particle size and size distribution can be controlled, leaving only catalysis time to be optimized.

As described earlier, a major processing challenge hindering high aspect ratio TSV Cu metallization is the deposition and performance of the barrier layer, which prevents copper diffusion into the TSV silicon. Because the seed layer requires a high temperature anneal after deposition to remove crystalline defects, an effective barrier layer must possess three major material properties: (1) high melting temperature, (2) low Cu diffusivity at elevated temperatures, (3) sufficient adhesion to both the insulation and seed layers. In addition, the skin depth limitations of RF devices require conductors with low permeability (μ). Titanium, tantalum, and their nitrides^53–56 have been used as barrier layer materials, largely because of their effectiveness in aluminum ULSI metallization. Traditionally, such layers are deposited by sputtering, but deposition is hindered in high aspect ratio TSVs by the shadowing effect, which can minimize or completely block sidewall deposition. In response, electroless barrier layer deposition has been proposed for several years,^28–32 with nickel and cobalt the most used base metal candidates due to their widespread industrial use and high temperature and electromigration resistance. They are alloyed with refractory metals such as rhenium, tungsten, and molybdenum to increase their high temperature resistance,^28–32 along with phosphorus and boron to reduce inductive effects.

The continued use of metallic based barrier layers, however, will be hindered by two distinct design limits. In CMOS devices, it is desirable to minimize the resistive contribution of RC delay from the barrier layer, while in RF devices, it is desirable to minimize the inductive contribution of LC delay and losses from conduction within the skin depth layer due to the barrier layer. In RC limited devices, advances in scaling will require thinner barrier layers. For example, it is estimated that for 14 nm node devices, barrier layers must approach 2 nm or less.¹⁵ However, the barrier thickness does not scale without significant diffusivity and resistance reliability issues. In LC limited devices, skin depth dependent signal propagation is constricted as frequency increases. As signal frequency increases in RF devices, the skin depth, δ, of the conductor approaches the TSV diameter, d_TSV, as scaling decreases. For example, in the SiC module described in Sec. I, the maximum copper skin depth (δ_max = d_TSV/2) corresponds to a usable frequency range of 8–30 GHz before skin effects dominate. As skin depth decreases as frequency increases, the ability for thinner barrier layers to protect diffusion while minimally contributing inductive and resistive effects to the device will again be compromised. Ultimately, it is the material limits of existing barrier materials drives our push toward nonmetallic barrier materials such as SAMs.

The advantages of a SAM barrier layer for TSVs are numerous: (1) binding groups that facilitate oxide insulator functionalization, (2), end groups suitable for catalysis, (3) selective patterning deposition, and (4) high temperature Cu diffusion protection, all at low processing temperatures (< 100 °C). Krishnamoorthy et al.²³ demonstrated the feasibility of the use of SAMs as barrier layers in ULSI integration processes, using bias thermal annealing. He concluded SAM layers with aromatic groups provide better barrier layer protection than aliphatic SAMs, based on the change in leakage current density over time. Several groups^45–48 have used 3-aminopropyltrimethoxysilane (APTMS), an aliphatic SAM layer tested in Ref. 22 as well as 3-aminopropyltriethoxysilane (APTES),^32,49–51 to electrolessly deposit barrier^32,50,51 and Cu seed^{45,46,49–51} layers into TSVs with aspect ratios as large as twenty.^50,51 Multilayers of APTMS with other materials can increase the Cu diffusion barrier.³³ Molecular dynamics studies emphasize the importance of ordered layers,⁵⁷ while experimental studies note the importance of solvents, in particular, the use of hydrophobic ones.³⁴ In addition, APTMS functionalized EL copper was recently shown to withstand copper diffusion in vacuum annealed samples ranging up to 700 °C.⁴⁷ Although there exists extensive research on the Cu_seed/APTMS and Cu_seed/APTES systems, we investigate the aromatic SAM (aminomethylaminoethyl)phenethyltrimethoxysilane (PEDA), for reasons we have detailed in Secs. IV A and IV B. It contains an aromatic ring, so should act as a good barrier when the layer is dense. We monitor density by the index of refraction and thickness to insure a single layer, using contact angle and ellipsometry.

Finite element modeling of vias can answer two simple questions: how important is the shape of the via and where is the current density highest, and what is the effect of a thin metal seed layer quality and composition that we need to electroless-deposit on SAM layers as a seed for copper electroplating. The qualitative result is that the current flows in the outermost surfaces of the via complex at high frequencies, so the seed layer quality is very important. The further these current-carrying regions are apart (up to a wavelength or so) the lower the inductance. The high magnetic permeability of a nickel layer significantly increases the via inductance for all thicknesses tested, down to the thinnest layer that can be controllably produced by electroless deposition. Thus, seed layer composition is important and the (easier) nickel layer cannot be used. We use Cu here and find that even a non-optimal copper layer has a small enough skin depth so that it carries most of the current at 10 GHz—with significant loss—so optimization is critical.

This section makes the well-known point that via shape matters independently of the materials properties, but it is important enough for a reminder. Modeling was performed with a 2D finite element program (FEMLAB by COMSOL). Four shapes were used. All shapes had the same total cross-sectional area. The shapes were: a circle of 10 μm diameter; four circles touching, each of 5 μm diameter; the four circles further apart, about 16 μm across the diagonal of a square; and a rectangle 5 μm wide. The first two are shown in Figs. 5(a) and 5(b), which also presents the current distribution, where the above qualitative statements can be seen to apply: the current lows at the furthest-out regions. The inductance roughly scales with the distance from center of the outermost-part of the via [Fig. 5(c)]. Of note is that the resistance does not scale in this manner, as the size of that outermost region also varies [Fig. 5(d)].

The material effect is seen clearly in a comparison of the Cu seed/via to one with a Ni seed layer. The single circular via, with 1/2 or 1/10 μm of Ni on the outside was used in the calculation. The performance is significantly worse than the pure copper via, as is shown in Fig. 6. This result points to the importance of material choice for electroless deposition onto a SAM layer to make a via: one must deposit Cu rather than Ni. We, therefore, show only copper deposition here, rather than other materials that have a more-developed electroless deposition history.

The results can also be understood from the viewpoint of the skin-depth, δ, which quantifies the distance that the current penetrates (1/e length) into the via. The skin depth for current flow is dominated by magnetic effects and should not be confused with the penetration depth of propagating waves into a surface, which is instead dominated by electric-field effects. For current, the formula is $δ= ρ π f μ$ assuming that the frequency $f≪ 1 ρ ϵ$⁠.⁵⁸ Here, ρ is the resistivity of the metal and ε its dielectric constant. For Ni as seen above, the formula gives a very small skin depth so that even 100 nm of Ni has a large effect. In fact, the skin depth of Ni, using a textbook resistivity of 6.99 × 10⁻⁸ Ω m and a relative magnetic permeability of 6, gives about 100 nm near 10 GHz. For copper, the magnetic permeability μ is near that of vacuum, μ₀. The limit on validity of the skin depth formula requires f << 10¹⁶. With textbook ɛ = −6220, we find it to be true for all relevant frequencies. Taking the textbook resistivity of 1.68 × 10⁻⁸ Ω m and a relative magnetic permeability of 1 for Cu, we find 652 nm as the skin depth. This is a little more than twice the “optimal” Cu thickness that we have determined (Fig. 6). The “optimal” resistivity is close to the textbook value, so the current is divided between the electroless and electro-deposited Cu in this case. Emphasizing our goal of optimization, we find that the worst-case resistivity in the optimization tests of Fig. 6 is almost 1000 time higher than the optimal, so the skin depth would be about 30 times smaller, near 20 nm and current would flow fully within the (high resistivity, nonoptimal) electroless-deposited material. Clearly, optimization of the initial electroless-deposited layers is important.

We have identified a barrier/seed system to seed complex, nonline of sight surfaces with a copper layer before further electrochemical growth to fill vias or small traces. At high frequencies, the conductivity of this seed layer is important, so it is important that its characteristics be optimized. Calculations of the skin depth at 10 GHz indicate that current is shared between the electroless Cu seed layer and the electrochemical fill layer for the optimal electroless conditions. However, the current would flow fully within the seed layer for some nonoptimized seed layers tested—and it would do so with high losses. We considered the variation of four parameters for optimization: catalysis deposition time, copper deposition time, film resistivity, and film thickness, and used film structure, adherence, and resistivity to find optimal parameter values. The base PEDA layer is straightforward to optimize, while the Pd catalyst layer strongly and qualitatively impacts both structural and electrical properties of the copper. We qualitatively and quantitatively evaluate these properties.

It is vital that the PEDA and catalyst layers are deposited as uniformly as possible. With a dense PEDA and even, well-distributed PD2 layers, too short a copper deposition time does not allow enough time for uniform growth across a uniform PD2 layer, but too long a deposition time creates copper overgrowth, with poor substrate adhesion. Optimal copper resistivity is reached for 15 min of PEDA deposition, 4–8 min of PD2 deposition, and 2–4 min of Cu deposition at 40 °C, yielding a ∼300 nm thick Cu layer. We are confident that the uniformity of these electroless-deposited copper layers is sufficient to meet the demands of 3D packaging applications—a “smart” seed layer for “simple” via holes, and other complex surface metallization needs.

This work was supported by AFRL-WPAFB (Grant No. FA8650-04-2-1619).

The authors have no conflicts to disclose.

All authors contributed equally in this work.

J. K. L. Peters: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – original draft (equal). G. D. Ashby: Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – original draft (equal). H. D. Hallen: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Supervision (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal).

J. K. L. Peters: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – original draft (equal). G. D. Ashby: Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – original draft (equal). H. D. Hallen: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Supervision (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.