Chemical mechanical planarization for Ta-based superconducting quantum devices

Tantalum is a promising superconducting material for improving the coherence time of superconducting qubits when used to form the capacitor and microwave resonators in superconducting circuits.¹ Recently, two research groups^2,3 have reported high coherence times in the range of 0.1–0.5 ms for transmon qubits made on sapphire substrates using α-Ta (BCC phase) for wiring. The higher coherence time in both reports was ascribed to the difference in native oxides present on Ta versus other metals (Nb and Al). However, in order to enable the fabrication of Ta-based qubits in a truly scalable process, it would be advantageous to develop processing on 300 mm Si substrates (which are commonly used for IC fabrication) and move away from smaller diameter sapphire substrates. This will need new processes to be developed while retaining the advantages provided by Ta for qubit coherence times. Creating chips on 300 mm wafers with qubits that are interconnected with Ta lines offers a scaling path for superconducting quantum computing.

In addition to its advantages for superconducting quantum computing, Ta is a possible candidate to replace Nb for applications in certain single flux quantum (SFQ) circuits. For SFQ circuits that are coupled to quantum circuits and operate at temperatures below 1 K, the lower superconducting transition temperature of Ta versus Nb is not an issue. Ta has other advantages over Nb: lower sensitivity to hydrogen than Nb (Ref. 4) and lower solid solubility of oxygen.⁵ The functioning of SFQ circuits depends on the self and mutual inductances of interconnects but such inductances are sensitive to fabrication process variation and the specifics of chip layout. Hence, the fabrication of SFQ circuits with a better process control than demonstrated previously, and leveraging a well-established design-rule manual can open the door to very large-scale integrated SFQ circuits. Ta is a widely used material in the CMOS fab; thus processes and consumables developed by the CMOS IC industry over the past two decades can be advantageously leveraged and modified to suit the purposes of superconducting circuits. For these reasons, it is feasible and timely to develop a controllable process for fabricating superconducting Ta interconnects, with predictable characteristics that can be relied upon by the circuit designer.

In this paper, we demonstrate for the first time the design of a chemical mechanical planarization (CMP) process to create damascene Ta patterns with line widths ranging from 100 nm to 3 μm, with a post-CMP nanowire thickness of 80–85 nm. We have established an optimal CMP process for Ta interconnect patterns, with good within-wafer uniformity and wafer-to-wafer repeatability, supported by electrical measurements and physical characterization including x-ray fluorescence (XRF), atomic force microscopy (AFM), scanning electron microscopy (SEM), and optical microscopy. We have established the basic elements of CMP-related design rules for Ta interconnects that can be utilized for both quantum computing and SFQ circuit applications. Designs using CMP require the incorporation of layout elements called cheese and dummy fill.⁶ The process margin associated with these layout elements was studied to establish the parameters within which good CMP performance can be expected.

In this section, the process sequence is described, and the desiderata for superconducting circuits using Ta are laid out. A SiO₂/SiN dielectric bilayer on a Si (100) wafer is patterned using 193 nm optical lithography followed by a reactive ion etch (RIE) process that creates trenches stopping on silicon, as shown in Fig. 1(a). The exposed silicon in the trenches is etched to deepen the trench into silicon, with sloped sidewalls that expose (111) planes in silicon, using a hydroxide-based etch. The sloped sidewalls help with filling sputtered metal into the trenches and avoiding the formation of seams that would be present with vertical trench sidewalls. The SiN hard mask was removed using hot phosphoric acid etch, as shown in Fig. 1(b). The SiN hard mask over SiO₂ allows for the full thickness of the oxide to be retained during the trench patterning process. The SiN hard mask can also be used for other patterns to be created on the wafer surface (for example, deep alignment marks for multilayer Ta interconnects) which are not used in this study. Following the removal of SiN, metallic films required for the interconnect (ALD TaN/Ta) are deposited on the surface, as shown in Fig. 1(c).

While Ta is an element widely used in the IC industry (as a part of the liner for Cu interconnects), the α phase of Ta is specifically necessary for superconducting logic and quantum applications. The α phase of Ta has a superconducting transition temperature of ∼3.2–4.3 K depending on the deposition conditions.^7,8 The formation of α-Ta is promoted by a variety of underlayers;⁹ a good underlayer choice is ALD TaN.¹⁰ Without the underlying layer, sputter deposition of Ta on oxide forms the β phase which has an extremely low superconducting temperature (∼mK).¹¹ The formation of α-Ta can be confirmed at room temperature by x-ray diffraction and resistivity measurements since it has about 7× lower resistivity than the β phase.^12,13

CMP of the metalized wafer results in metal-filled trenches, as illustrated in Fig. 1(d). The oxide hard mask is only partly removed during CMP—with the exact amount remaining being a function of the CMP process being developed.

The thickness of Ta after CMP is completed should be greater than its penetration depth in order to limit dissipative losses when used in superconducting circuits such as SFQ circuits and superconducting resonators.¹⁴ The surface of the Ta film roughly duplicates the topography when it is sputtered onto a surface with patterned trenches. Since the ratio of removal rates at the low areas to the removal rate at high areas is not zero, it is necessary to give the CMP process enough incoming thickness to accomplish planarization. The specific overburden that is required for a given incoming topography is dependent on slurry and pad specifics. As a rule of thumb, the deposited thickness should be at least 1.5× nm, and preferably around 2× nm for incoming topography of x nm. In the case of Ta, film stress created during the deposition process precludes the deposition of a very thick film; hence, the starting thickness for CMP also needs to be chosen with care.¹⁵ 

An optimized CMP process leaves the Ta surface locally smooth and the wafer surface planar (within a few nanometers) along with good uniformity from the center to the edge.¹⁶ Such a planar surface makes the deposition and patterning of the next layer of interconnect easier and more controllable with associated advantages in SFQ circuit performance. Metal CMP relies on having as uniform a pattern as possible across the wafer surface since the CMP process acts simultaneously on all the materials exposed, each of which necessarily has a different local CMP rate. This is particularly important after the field overburden is cleared, and Ta, ALD TaN, and SiO₂ are all simultaneously exposed to the slurry and pad. Therefore, variations in the local areal density of Ta features will impact the CMP process locally. From the process engineer’s perspective, a uniform Ta pattern density is desired (irrespective of its specific value), where Ta pattern density or metal density is typically defined as the fraction of the area occupied by Ta patterns.⁶ In contrast, the designer would appreciate the flexibility afforded by permitting any value of the local Ta pattern density. The compromise that has been used in the IC industry, and which we have adopted, is to choose the average pattern density to be as close to 50% as possible.

Dummy patterns are automatically placed in areas without designed Ta features in order that the average pattern density is closer to 50%. The use of dummy patterns is called “dummy fill.” As a result of uniform local metal pattern density (and post-CMP metal thickness), the self-inductance of the conductors is more uniform and predictable (both within a chip and from design-to-design). This will help with the modeling of inductances and improving the ease of circuit design in SFQ circuits. Due to these considerations, we chose a damascene metal CMP approach to fabricate the patterned structures with dimensions varying from 100 nm to 3 μm, in preference to patterning metal with a RIE process.

Line widths were measured on 300 mm wafers at various points during the fabrication sequence using a critical dimension scanning electron microscope, equipped with automated pattern-recognition capability. Measurements made across the wafer surface after lithography, RIE, and CMP are summarized in Fig. 2. Figure 2(a) shows the variation of line width as a function of radial position on three wafers at the three steps that affect the pattern width. The within-wafer nonuniformity of the photoresist line width is <2%. The uniformity worsens after RIE for wafer radii higher than 75 mm, while still retaining wafer-to-wafer repeatability. The lot-to-lot variability is <2% for each process step, based on the data collected for 22 lots (73 wafers) over a period of 8 months, as shown in Fig. 2(b). The term “lot” refers to a batch of identical wafers or ICs that are processed at the same time and under the same conditions, carrying chips of a specific version of a device. The point corresponding to each lot presents the wafer average of post-RIE CD for all the wafers that ran in that lot. Figure 2(d) shows the result of a topography measurement after an anisotropic Si etch. The scan is performed along the black line shown in the image of the AFM feature (which includes line widths varying from 100 nm to 5 μm) as in Fig. 2(c). The trench depth of the 100 nm wide line is not resolvable due to the limitation of AFM tip size but all other line widths are resolvable and confirm a trench depth of 110 nm, as shown in Fig. 2(d). Trench depth was the same (within measurement error of ±5 nm) across the wafer, between wafers in the same lot, and from lot-to-lot (based on data from wafers in five different lots, processed over a period of 4 months).

α-Ta films were deposited at a 300 mm scale using magnetron sputtering in a multichamber sputter deposition tool. Characterization of this film is done with a bilayer film on silicon as shown in Fig. 3(a). A 3 nm thick underlayer of the ALD TaN film, deposited using an atomic layer deposition with a commercially available Ta precursor, serves two purposes. First, it acts as a reaction barrier between Ta and Si.¹⁷ Second, it helps to promote the formation of α-Ta.¹⁰ 

Figure 3(b) shows the sheet resistance map obtained from 49 points distributed across the wafer surface with an edge exclusion of 3 mm. The calculated within-wafer resistance nonuniformity (one standard deviation as a percentage of the median resistance) is better than 5%. The resistivity is 23 μΩ cm, calculated from the resistance and x-ray reflectivity (XRR) thickness measurement, providing one confirmation that Ta is present in the α-phase.^12,13 Figure 3(c) shows the in-plane and out-of-plane XRD, providing the second confirmation, that Ta has the body-centered cubic crystal structure expected of α-Ta, with a lattice constant of 3.3 Å. Table I lists all the film properties of blanket Ta films at room temperature.

In most 300 mm CMP processes, a combination of hard pad and soft pad is typically used since it permits the desirable aspects of both pads to be leveraged such as a higher polish rate, better planarization, and in situ process endpoint enabled by the hard pad with low defectivity of the soft pad when used as the last step of a multipad CMP process.¹⁸ The CMP process design considerations include dividing the process between the hard pad and soft pad, and the choice of slurry to be used on each polish pad.¹⁸ It should be noted that commercial slurries are designed with many goals in mind, including removal rate, the ratio of removal rate between various materials that are to be planarized, static etch minimization, corrosion protection, and overall low defectivity. These design considerations influence the choice of the abrasive particle and the chemistry package (oxidizer, chelating agents, surfactants, and corrosion inhibitors). These formulation specifics are closely held and not discussed in open literature. In this study, a commercially available alumina-based slurry was used for the hard-pad planarization step, with a commercially available silica-based slurry for the soft-pad buff step. Both are provided by their suppliers to the CMOS industry as slurries that can accomplish Ta removal.

After the removal of SiN with hot phosphoric acid, the step height of the trench is correspondingly decreased from 110 to a value of 90 nm [Fig. 1(b)]. The preferred thickness of incoming Ta for this step height is about 180 nm, for the reasons described previously. During the hard-pad polish step, the reflectance of the wafer surface is monitored with a red laser that shines through a transparent window integrated into the pad. A user-defined wafer average metric of the reflectance is plotted as a function of the polish time as shown in Fig. 4. When a user-selected criterion is reached (as defined by the pair of blue boxes in Fig. 4), the CMP tool declares the process end-pointed and moves on to an overpolish step of a user-defined duration. The endpoint criterion is usually developed iteratively and includes testing with multiple patterned wafers to ensure it is robust in “catching” the endpoint. In this process, the endpoint criterion is that the slope of the reflectance curve exceeds a target value twice (for robustness). After the endpoint is triggered (the dotted vertical line in Fig. 4), the process is continued for 40 s of the overpolish step.

A test wafer that went through the endpoint followed by the overpolish was cross-sectioned and imaged with SEM to verify the wafer state. As shown in Fig. 5(a) (schematic cross section) and Fig. 5(b) (SEM cross section), the Ta surface has been locally planarized, leaving a thickness of ∼40 nm on the field. The hard-pad process leaves microscratches on the surface, and hence, it is desirable to leave some overburden on the field at the end of the hard-pad process, allowing microscratches to be buffed away by the subsequent soft-pad polish step with minimal removal of silicon oxide in the field areas.

Figures 5(c) and 5(d) show the final schematic and SEM cross section after both steps of the CMP process are completed. It can be seen that the loss of oxide in the field areas is as low as 5–10 nm (starting thickness of oxide in the field area is ∼50 nm, and the thickness is ∼43 to 45 nm when measured by spectroscopic ellipsometry post-CMP).

CMP rates on blanket wafers do not translate in a straightforward fashion to rates on patterned wafers. In order to accelerate the process development on patterned wafers, XRF spectroscopy was used. In particular, we used energy-dispersive XRF equipped with a Mo Kα x-ray source with pattern-recognition capability to monitor the Ta L_α1 signal at ∼8.15 keV (Ta XRF). For wafers that were processed through both the hard-pad and soft-pad steps, the trench pattern is revealed. In this case, we added an optical pattern-recognition step in the XRF measurement to land on the targeted measurement area.

A 500 μm region with dummy fill was measured by XRF. Figure 6(a) shows a decrease in Ta XRF signal intensity as polishing time increases, reflecting the removal of Ta atoms as CMP progresses. Each point on the graph represents the average of four measurements taken at different (x, y) co-ordinates, but with the same wafer radius. Figure 6(b) shows the Ta XRF intensity (after both the hard-pad and soft-pad CMP steps) as a function of radial position from a wafer with 200 nm thick Ta (pre-CMP). The data indicate <4% variation over the entire patterned wafer with the optimized CMP process developed in this study.

This section details how features on the wafer can be studied to reveal the suboptimal CMP processes. The examples presented in this section are derived from earlier iterations of process development, or deliberate deviations from optimal conditions that were tested to determine the process window. Figure 7 shows one of the examples where there are metal residues on the field when the polish parameters are not optimized. Figure 7(a) shows the optical microscope image of the patterned feature with a dummy metal fill around the patterned features. It can be seen that the metal residues are present on the dummy metal region which is due to nonoptimal CMP process parameters. Figure 7(b) shows the SEM micrograph of an example where the Ta metal residues are present even on the patterned feature, and Fig. 7(c) shows a higher magnification view of the Ta metal residue present on the patterned feature, all showing the importance of establishing an optimized CMP process.

As described previously, the deposited film thickness is usually twice the height difference that needs to be planarized. Figure 8 shows a case when the deposited metal thickness is deliberately chosen to be thinner at 150 nm rather than 200 nm. Figures 8(a)–8(h) show the comparison of patterned features (post-CMP) at the wafer center and wafer edge for the two different thicknesses of Ta. Here, we observe more Ta metal residues for the wafer with 150 nm thick Ta, whereas the features are clean for the wafer with 200 nm thick Ta for the same CMP process. It can also be noted that the wafer edge is more prone to such residue defects for the chosen CMP process.

Several electrical and physical properties need to be well characterized and produced in a repeatable and predictable fashion for a designer to use Ta lines in superconducting quantum or superconducting logic circuits. In addition to properties related to superconductivity (transition temperature, coherence length, penetration depth, and critical current density), it is also important to provide the designer with the resistance per square of various line widths, along with the maximum expected range in this resistance due to within-wafer and wafer-to-wafer variations, as well as due to local metal density variations. Mutual and self-inductance values are usually predictable using geometry-based simulations and also, must be provided to the designer. For superconducting circuits that operate at cryogenic temperatures, many low-level leakage mechanisms (such as conduction through silicon) that are operative at room temperature are absent at operating conditions when thermally excited charge carriers are “frozen” out. Hence, leakage measurements at room temperature are required to assure the designer that shorts associated with the residual metal are never present, or particulate contaminants do not accidentally connect two superconducting lines on the chip. In Secs. III A–III H, the results of our process development are discussed, with reference to resistance and leakage behavior, in addition to the establishment of dummy block and cheese block rules.

Figure 9 shows the sheet resistance measurements of Ta serpent lines as a function of line width, line spacing, and metal density. Figure 9(a) shows the wafer map with the squares representing individual dies (chips) of dimensions 12.5 × 15.5 mm². The squares marked by “x” represent 26 sites where the electrical characteristics were measured. It can be seen from Fig. 9(b) that the sheet resistance of Ta lines remains close to 2 ohms/sq for line widths varying from 100 nm to 3 μm and line spacing varying from 100 nm to 1 μm. The within-wafer nonuniformity (standard deviation, expressed as a % of the mean value) is determined by measurements taken from 26 dies distributed across the wafer [Fig. 9(a)] for each isolated line width with two measurements taken from each die for the same copy of the device but at different locations on the die, as shown in Fig. 9(c). It can be seen that the sheet resistance nonuniformity is less than 12% for all line widths. The improvement of uniformity as the line width increases can be explained by invoking a fixed line width variation post-RIE of 5 nm (independent of the line width). This gives rise to a decreasing % variation as line width increases. This decreasing %NU trend is added to a CMP-related nonuniformity of ∼5% that is line width independent. Figure 9(d) shows the sheet resistance as a function of % metal density. The sheet resistance remains close to 2 ohms/sq for all metal pattern densities up to >90%.

As described previously, the room temperature leakage measurements of superconducting circuits served a different purpose than such measurements would have for CMOS integrated circuits operating at room temperature. Leakage measurements in this case are designed to confirm that metallic residues (say due to underpolish) are not present on the wafer. They also serve to confirm that particulate defects that can short two adjacent lines at room temperature do not exist. Such defects cause the leakage to rise to the current compliance limit chosen for room temperature testing. It is also useful to confirm that the measured leakage for a given structure is largely invariant across the wafer diameter and from wafer-to-wafer, as another indication of process control.

Figure 10 shows the room temperature leakage characteristics of comb-serpent structures for line space varying from 100 nm to 1 μm and line widths varying from 100 nm to 3 μm. Figure 10(a) shows the SEM micrograph of a comb-serpent structure of dimensions 75 × 100 μm² across which the leakage is measured. Figure 10(b) shows a higher magnification view of the same comb-serpent structure. In contrast, Figs. 10(c) and 10(d) show an example of the comb-serpent structure with residual Ta left when the CMP process is not optimal. Such defects will result in excessive leakage currents being measured, triggering a compliance limit during a test, as shown in Figs. 10(e) and 10(f) (expressed as nA/μm). Leakage values of less than 1 nA/μm are observed for all the line spacings tested at all the points on the wafer, as shown in Fig. 10(e). Figure 10(f) shows leakage as a function of line spacing for different line widths. While the leakage is low for all the structures shown, it is not surprising to note that it is higher for structures with a smaller line space. When the applied voltage is the same for all the tested structures, smaller spacing results in a higher electric field, resulting in a higher leakage due to charge carrier transport at room temperature.

Figure 11 shows the results of local topography measurement using AFM of a 2 μm wide line after the CMP is completed. Topography is less than 1 nm over a 2 μm wide line, as shown in Fig. 11(b), for the region marked in a blue dashed line in Fig. 11(a). The second trace indicates topography across the 15 μm width of the scanned area including the dummy fill region, as shown by a green dashed line in Fig. 11(a). It can be seen that the dummy fill pattern protrudes less than 1 nm from the oxide field area.

Figure 12 shows the topography across a 35 μm wide AFM test feature [inset of Fig. 12(a)] having line widths varying from 100 nm to 5 μm. The onset of CMP dishing depends on the geometry of the pattern such as the line width and the area fraction of Ta. CMP dishing of less than 2 nm is observed for each line in the AFM test feature at both the wafer center [Fig. 12(a)] and wafer edge [Fig. 12(b)]. The overall topography is less than 5 nm (excluding noise in the AFM scan data)—this bodes well for building multiple layers of Ta interconnect in an oxide matrix for SFQ circuits.

In regions with no metal traces placed by the designer, it is necessary to add nonfunctional patterns (called “dummy fill”), in order to have a uniform metal density across the die (and wafer).⁶ We have chosen a dummy fill unit cell composed of 500 nm square Ta islands, with offsets, as shown in the schematic Fig. 13(a), and filled the areas with no circuit patterns with a dummy fill, as shown in the SEM image of Fig. 13(b). The designer would need to know how close the dummy fill comes to patterned lines. In our design-rule manual, this value is set to 6 μm. Additionally, in some regions of the circuit layout, it may be necessary to disallow dummy fill. This is accomplished by a separate dummy block layer in the chip design layout file where polygons are placed on areas where automated dummy fill is to be excluded. The residual metal could change the flux distribution and resonant frequency of superconducting microwave resonators and superconducting qubits, and hence, a robust CMP process with an associated design rule that eliminates the extraneous residual metal is necessary.

In a fashion analogous but opposite to dummy fill, solid metal lines laid out by the designer (that are wider than a certain value), are subjected to automated routines that create holes in a prespecified pattern. With such “cheesing” of wide metal lines, the local metal density is reduced from 100% to a value closer to 50%. Wide metal lines are cheesed with holes of dimensions 500 × 500 nm², in a pattern as shown in Fig. 13(c) with the SEM image of the cheesed line shown in Fig. 13(d). The designer would also need to know how close to the edge of the circuit trace the cheesing holes are allowed to come, and the resultant impact on line resistance. Experimental structures to determine these values are described in Sec. III F.

Figure 14 shows the patterned structures with dummy block areas having dimensions varying from 6 to 150 μm². The regions with dummy block areas up to 75 μm² have clean features [Figs. 14(a) and 14(c)] whereas the regions with 150 μm² area have residual Ta metal leftover, as shown in Fig. 14(e). Figures 14(b), 14(d), and 14(f) are the corresponding layout images. These data support a design rule that the dummy block area cannot be larger than 75 μm².

The effect of cheesing is measured using electrical measurements in the structure labeled “CMD” as shown in Fig. 15(a). In this structure, the width of the uncheesed Ta line (cheese block) is systematically varied. Images from the layout file are shown in Figs. 15(b) and 15(c) for two different widths of the cheese block. Immediately next to the uncheesed Ta line (and separated by 110 nm space), a thin line (110 nm) was placed for two-point resistance measurement, as shown in the SEM image of Fig. 15(c). This 110 nm wide Ta line is used as a “canary” to detect the resistance change due to the cheese block.

Figure 15(e) is a plot of the normalized resistance as a function of cheese block width at the wafer center, and wafer radii of 52.79, 104.69, and 126.52 mm. The normalization is with respect to the resistance at a 2 μm cheese block width. The resistance increased by ∼8.5% as the cheese block width was increased from 2 to 10 μm for all radii. In order to keep the resistance change to <5%, the limiting width of the cheese block has been set at 6 μm.

The optimized CMP recipe was subsequently tested on four wafers over a period of two months. The isolated line sheet resistance results were repeatable, with all wafers showing the same trend as a function of line width, as shown in Fig. 16(a). Figure 16(b) shows that the leakage (for a line spacing of 300 nm) was low at all the measured sites on all wafers. Figure 16(c) compares the sheet resistance for a 1 μm wide serpent (spaced 300 nm away from unrelated metal lines) for these wafers, providing an illustration of the degree of repeatability observed with this process. The influence of the dummy block and cheese block on CMP performance was also the same in terms of the maximum allowed dimensions (75 μm²) with clean features and the impact of the cheese block width on Ta line resistance, normalized to resistance with a 2 μm cheese block width [Fig. 16(d)].

We developed a process flow for creating damascene α-Ta patterns (∼85 nm thick) for the first time on a 300 mm wafer scale. The results presented here form a part of a 300 mm Ta CMP design-rule manual that specifies a minimum line width and space, maximum dummy block area, and maximum uncheesed line width, and also provides the electrical characteristics of Ta lines of line widths ranging from 100 nm to 3 μm. The process described here can be utilized for making superconducting resonators and for superconducting interposer chips to connect multiple chips. While the process was tested in a single layer, the topography measurements post-CMP suggest that SFQ circuits with multiple layers can utilize these results. The CMP process employed an optical endpoint during the hard-pad polish step, followed by a fixed time overpolish on a soft pad. This process was tested over a period of two months to test the repeatability. Dummy block regions with dimensions up to 75 μm² were found to be safe, without any residual metal observed. The maximum cheese block width was set to 6 μm. Leakage value of less than 1 nA/μm is reported for a 50% metal density. Post-CMP topography was determined to be less than 5 nm at all points on the wafer for all the line widths tested. Serpent sheet resistance was found to range from a minimum of 0.44 ohms/sq for 3 μm lines to 1.9 ohms/sq for lines of 400 nm width. Within-wafer resistance nonuniformity was determined to be less than 12% for all line widths. In future studies, the post-RIE CD uniformity will be improved. During CMP processing, a first wafer effect was observed—the resultant increase in variability can be addressed by using one “seasoning wafer” ahead of the product wafers. In addition, it is likely that the long-term repeatability of post-CMP resistance performance can be further improved by implementing a “rate-qualification” procedure and replacing the fixed time polish, used in this study, with a polish time that takes into account the rate decay due to pad aging.

The support of this study by the Air Force Research Lab (AFRL), Rome, NY, through Contract Nos. FA8750-19-1-0031 and FA864921P0773, is gratefully acknowledged. The authors gratefully acknowledge the help provided by Matthew Bracken of NY CREATES for cross-sectional analyses by scanning electron microscopy.

The authors have no conflicts to disclose.

Ekta Bhatia: Conceptualization (equal); Data curation (lead); Formal analysis (lead); Investigation (lead); Methodology (equal); Validation (lead); Visualization (lead); Writing – original draft (lead); Writing – review & editing (equal). Soumen Kar: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – review & editing (equal). Jakub Nalaskowski: Conceptualization (equal); Data curation (supporting); Formal analysis (equal); Investigation (equal); Methodology (lead); Validation (equal); Visualization (equal); Writing – review & editing (equal). Tuan Vo: Methodology (equal); Writing – review & editing (equal). Stephen Olson: Formal analysis (equal); Validation (equal); Visualization (equal); Writing – review & editing (equal). Hunter Frost: Formal analysis (equal); Validation (equal); Visualization (equal); Writing – review & editing (equal). John Mucci: Methodology (equal); Writing – review & editing (equal). Brian Martinick: Methodology (equal); Writing – review & editing (equal). Pui Yee Hung: Methodology (equal); Writing – review & editing (equal). Ilyssa Wells: Methodology (equal); Writing – review & editing (equal). Sandra Schujman: Methodology (equal); Writing – review & editing (equal). Satyavolu S. Papa Rao: Conceptualization (lead); Data curation (equal); Formal analysis (lead); Funding acquisition (lead); Investigation (equal); Methodology (equal); Project administration (lead); Resources (lead); Supervision (lead); Validation (lead); Visualization (lead); Writing – original draft (equal); Writing – review & editing (lead).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

Ekta Bhatia has been a research scientist in Quantum Technologies at NY CREATES in Albany, NY, USA since 2021. She is part of a team developing materials and devices for superconducting quantum technologies. Her current research efforts focus on the 300 mm scale fabrication of high-performance superconducting quantum computing circuits, single-flux-quantum logic circuits, and superconducting optoelectronics for neuromorphic computing.

Previously, as a post-doctoral researcher at the Laboratory for Physical Sciences (LPS) at the University of Maryland, USA, she developed processes using CVD and PVD for materials for quantum computing materials. She also investigated loss mechanisms in superconducting microwave resonators to guide the qubit design. In 2018, she worked as a visiting researcher in the device materials group at the University of Cambridge, UK. There, she worked with Professor Jason Robinson and Professor Zoe Barber on the study of spin-triplet supercurrents in magnetic Josephson junctions and SQUID devices for superconducting spintronics. She received her Ph.D. in Physics in 2020 from the National Institute of Science Education and Research (NISER), Homi Bhabha National Institute, India. During her Ph.D., she demonstrated the spin-polarized triplet supercurrents in magnetic Josephson junctions using novel device structures. She is the lead author/co-author of nine publications and is a member of IEEE and the American Vacuum Society.

Soumen Kar received his B.Sc. in Physics (Honors) degree from Vidyasagar University, West Bengal, India in 2004 and M.Sc. in Physics degree from Vellore Institute of Technology, Vellore, Tamil Nadu, India in 2006. He received his M.S. in Cryogenic Engineering in 2009 and Ph.D. in Applied Superconductivity in 2017 from the Cryogenic Engineering Center at the Indian Institute of Technology, Kharagpur, India.

At present, he is a process integration engineer at AIM Photonics/RF SUNY, Albany, NY and during from Jul’21 to Feb’23, he was a research scientist in Quantum Technologies at NY-CREATES/RF-SUNY, Albany, NY, USA. Since from October 2016 to June 2021, he was a materials engineer and principal investigator of DOE-SBIR projects in AMPeers LLC, Houston, Texas. In AMPeers, he scaled up highly flexible REBCO-based round wires to 60 m and developed round REBCO wire architectures to achieve high engineering current density in high magnetic fields at 4.2 K. He has been the lead person in the development of the symmetric REBCO tapes and STAR wires. Since from May 2014 to June 2020, he was working as a Research Scientist in the Mechanical Engineering Department at the University of Houston, and from July 2020 to June 2021, he was working as a research scientist in the Electrical and Computer Engineering Department at the same University. In 2019, Dr. Kar became a senior member of IEEE. His research interests are Josephson junctions, superconducting/quantum materials and devices, Si Photonics 2.5D/3D HI, SNSPD, quantum photonics, CMOS, non-CMOS devices, superconducting qubit/nanowire on 300 mm wafer scale, flexible HTS wires, and HTS power/energy applications.

Hunter Frost received his B.S. in Nanoscale Engineering, with a minor in Applied Mathematics, from SUNY Polytechnic Institute’s College of Nanoscale Science and Engineering in 2020. While pursuing his undergraduate degree, Hunter developed co-sputter RF-PVD deposition processes for high ionic conductivity solid-state electrolytes (including LiPON and LiAlTiPO) for use in all-solid-state lithium-ion batteries. Hunter is currently pursuing a M.S/Ph.D. in Nanoscale Engineering at SUNY Polytechnic Institute’s College of Nanoscale Science and Engineering, in collaboration with NY CREATES and Tokyo Electron, Ltd., with a research focus on the effect of material and interface quality on the cryogenic performance of superconducting quantum circuits at a 300 mm wafer scale, as well as the application of atomic layer deposition and RF-plasma treatment to the fabrication of such devices.

In addition to his academic career, Hunter has held a process engineering position at TEL Technology Center, America, LLC since 2019, where he has developed novel thin film deposition processes for next-generation logic and memory devices and beyond-CMOS technologies.