Implementation of high-performance and high-yield nanoscale hafnium zirconium oxide based ferroelectric tunnel junction devices on 300 mm wafer platform Free

Since CMOS technology reached its fundamental scaling limits, some emerging nonvolatile memory (NVM) concepts have made significant progress in recent years.^1–5 In contrast to volatile memories, which require constant power to retain its state; NVM devices allow for data retention when not powered.⁶ Modern day technology imposes different requirements on memory devices, e.g., high density data storage, low cost, fast read and write speeds, long data retention, and low power consumption.^7,8 Various novel concepts, architectures, materials, and operation principles are being explored in NVM technology to fulfill these requirements. One such promising nonvolatile memory technology is the ferroelectric tunnel junction (FTJ). An FTJ is a two terminal nonvolatile memory device with two metal electrodes sandwiching a thin ferroelectric layer allowing quantum mechanical tunneling through it.⁹ The switchable polarization of the ferroelectric layer enables a significant change in tunneling resistance of FTJ devices.¹⁰ Unlike FRAM, FTJ has a nondestructive read-out process since the tunneling current is sensed and the polarization state in ferroelectric switching layer is retained.¹¹ In addition, FTJ devices offer a significant advantage with regard to superior scaling capability since scaling in these devices is not limited by the stored amount of polarization charge.¹² One of the key challenges in manufacturing high-performance FTJ devices is the trade-off between remanent polarization and sizeable quantum mechanical tunneling current magnitude. The ferroelectric switching layer should be thin enough to achieve sufficient tunneling on-current; however, the magnitude of remanent polarization in these thin films is small impacting tunneling electroresistance (TER) ratio negatively and creates a major hindrance in reliable FTJ device design.¹² Other challenges, such as low TER ratio, stress induced leakage current based endurance/lifetime limitation,¹³ and retention degradation due to depolarization field,¹⁴ remain on pathway to large-scale commercial adoption of FTJ technology in the semiconductor memory industry.

Some studies in the past few years have tried to address some of these FTJ challenges. Goh and Jeon observed almost zero TER with symmetric TiN/HZO/TiN FTJ stack and demonstrated a much improved TER ratio (>6) by changing the bottom electrode to Ge.¹⁵ Ryu et al. showed that using p-Si as a bottom electrode over metal based electrodes could significantly improve the FTJ TER ratio and they demonstrated a TER ratio of ∼5 for Ti/Au/Al₂O₃/HZO/p-Si based FTJ structure.¹³ Max et al. achieved an excellent TER ratio (∼10) for 12 nm thick HZO based FTJ, but >4 V of programming voltage was used to reliably switch those FTJ devices,¹⁶ making them nonideal for low power NVM applications. All these studies mentioned above focused on development of large size, i.e., μm scale FTJ cells. At the nanoscale, loss of reliable control of ferroelectric properties is one of the major challenges in nanoscale implementations of FTJ, which severely limits its potential to be considered as industrially viable nonvolatile memory.¹² Investigating switching performance, reliability, and a statistically significant large-scale development of high-performance/yield nanoscale FTJ devices is still missing in current research. With that goal, in this work, hafnium zirconium oxide (HZO)-based 100 × 100 nm² FTJ devices were implemented on a 300 mm wafer platform, using SUNY Polytechnic Institute’s 65 nm CMOS process technology. Key insights into nanoscale FTJ switching dynamics and reliability are presented based on optimization of HZO based stack fabrication and programming approaches. Multi-level-cell (MLC) behavior for improved storage density and full wafer scale key switching metrics for fabricated FTJ devices are investigated.

FTJ devices (with TiN/HZO/TiN stack) were integrated in between metal (M1) and Via 1 (V1) layers in CMOS back end of the line process flow. Figure 1 shows a simplified process flow for FTJ device integration on 300 mm wafer platform. Fabrication of the FTJ device stack started with a TiN bottom electrode (BE) layer patterned using a subtractive integration scheme on top of M1 metallization layer, Fig. 1(b). The via insulator layer Si₃N₄ was then patterned around BE layer, Figs. 1(c) and 1(d). On top of the bottom electrode, a conformal thin layer of 5 nm Hf_0.5Zr_0.5O₂ switching layer was deposited via atomic layer deposition (ALD) at a deposition temperature of 250 °C followed by a 5 nm TiN layer, deposited via ALD, Fig. 1(e). A final 50 nm TiN top electrode (TE) layer was then deposited using physical vapor deposition, Fig. 1(e). Afterward, a postdeposition 60 s N₂ anneal at 450 °C was done to drive the HZO into the ferroelectric phase.

The entire FTJ device stack was then lithographically patterned and etched using a custom-designed reactive ion etch process. A Si₃N₄ mask layer was deposited on top of TiN TE, Fig. 1(f), to protect the device top surface from subsequent V1/M2 patterning steps, Fig. 1(g). A standard state of the art dual-damascene Cu V1/M2 module and CMP concludes the FTJ integration, Figs. 1(h) and 1(i). Cross-sectional transmission electron microscopy (TEM) imaging along with energy dispersive x-ray spectroscopy (EDS) analysis of the fabricated FTJ device stack confirmed the targeted thickness and composition of deposited films with low interface roughness [Figs. 2(a) and 2(b)]. The scaling of the BE is also observed at 100 nm with an overlay of the SL/TE.

Figure 3(a) shows electrical polarization hysteresis measurement of TiN/Hf_0.5Zr_0.5O₂/TiN FTJ device stack. The device shows a good ferroelectric response with an extracted remanent polarization (P_r) of ∼15 μC/cm² and a coercive switching field of 2.25 MV/cm. The polarization hysteresis characteristics and remanent polarization were measured post 100 wake-up field cycles with 10 kHz frequency Positive-Up-Negative-Down (PUND) pulses. The observed ferroelectric behavior in HZO based FTJ devices is attributed to the presence of the noncentrosymmetric orthorhombic phase¹⁷ as confirmed by grazing incidence x-ray diffraction measurements shown in Fig. 3(b). Other structural phases observed include monoclinic and tetragonal phases. The device was set in up- or down-polarization state with PUND positive or negative pulses, respectively, with a maximum pulse amplitude of 3.5 V. After programming the devices into a certain polarization state, an I-V sweep was performed. Figure 3(c) shows a typical I–V characteristic of an FTJ device. Observably, the maximum read voltage applied (0.75 V) was kept smaller than the coercive voltage (∼1 V) to prevent change in programmed polarization state and corresponding switching state in FTJ devices. The up-polarization state (programmed with positive pulses in PUND waveform) sets the device in high conductance on-state, yielding an on-current density of 0.08 A/cm² at a read voltage of 0.75 V. An off-current density of 0.035 A/cm² was achieved due to down-polarization state (programmed with negative pulses in PUND waveform) of FTJ devices, yielding a TER ratio of ∼2.28. Figure 3(d) shows polarization endurance measurements of the device up to 10³ switching cycles in which the up and down remanent polarization states are programmed at write voltages of ±3.5 V, respectively. The device exhibited a weak wake-up effect up to 500 switching cycles followed by polarization fatigue and eventual hard breakdown of devices.

The TER ratio for fabricated MIM TiN/HZO/TiN FTJ devices was limited by off-state leakage current and not enough band tuning at HZO/TiN interface to facilitate a high tunneling transmission coefficient.¹⁸ To improve device performance, a modified FTJ stack was implemented in which we separated the ferroelectric switching layer and tunneling layer. A schematic of the modified FTJ stack is shown in Fig. 4(a), in which 2 nm thin Al₂O₃ tunnel barrier layer was inserted between the bottom electrode TiN and ferroelectric switching layer HZO. Figure 4(b) shows the polarization hysteresis characteristics for the modified FTJ stack with Al₂O₃ layer and a comparison with conventional FTJ stack without Al₂O₃ layer is also shown. The thin Al₂O₃ oxide layer results in an additional voltage drop across it, and, hence, an increase in coercive voltage (∼1.15 V) and a reduction in maximum achieved polarization (∼12.5 μC/cm²) can be observed for the same pulse amplitude when compared with the same for FTJ stack without Al₂O₃ layer. An increase in coercive voltage also allows for an increase in read voltage, which increases FTJ tunneling current.

The impact of the inserted tunnel barrier layer on FTJ performance can be better understood from the energy band diagram schematic in Fig. 5(a). With application of positive write pulse amplitude, the polarization in ferroelectric HZO layer is pointed toward Al₂O₃ layer, i.e., up-polarization state, resulting in downwards band bending in HZO. Subsequent positive read voltage also enables sufficient band bending in Al₂O₃ layer creating a triangular potential profile, which facilitates electron tunneling from bottom to top electrodes. Negative write pulse sets the device in the down-polarization state in which the polarization in ferroelectric layer is pointed toward the top electrode, and the upwards band tilt in HZO prevents a large number of electrons to tunnel through the oxide layer. The Al₂O₃ layer acts as an additional tunnel barrier layer in the off-state causing further reduction in the tunnel transmission coefficient. Hence, significant tunneling conduction is expected for up-polarization state whereas, the down-polarization state, programmed with negative write pulse should allow for a small tunneling current to flow in FTJ devices. This impact of Al₂O₃ tunnel layer is validated through measured current-voltage characteristics of FTJ devices shown in Fig. 5(b) where a significant increase (∼1.5 times) in on-current density and reduction in off-current density (∼1.45 times) were observed when compared to conventional FTJ stack without Al₂O₃ layer. At a read voltage of 0.75 V, the up-polarization state in ferroelectric layer resulted in a device on-current density of 0.12 A/cm². The corresponding off-current density due to down-polarization was extracted to be 0.024 A/cm² yielding a TER ratio of ∼5. Hence, a 2.2× improvement in device TER ratio was achieved with Al₂O₃/HZO bilayer based FTJ structure.

To demonstrate that the improvement in on-current density is due to enhancement in tunneling current, we investigated the conduction mechanism in TiN/Al₂O₃/HZO/TiN FTJ devices, shown in Fig. 6. We observed that for low applied field (E < 0.4 MV/cm), the plot of ln(J/E²) shows logarithmic variation with 1/E [Fig. 6(a)], which indicates that the device exhibits direct tunneling (DT) conduction. When the applied electric field exceeds a critical field, a transition from direct tunneling to Fowler–Nordheim (F–N) tunneling regime occurs as shown in Fig. 6(b). This transition field was extracted to be ∼0.4 MV/cm beyond which ln(J/E²) decreases linearly with 1/E, an indication of device operation switching in F–N tunneling conduction regime. The relationship between ln(J/E²) and 1/E governing both tunnel conduction processes can be understood from the following set of Eqs. (1)–(4):¹⁹ 

Direct tunneling regime (E < 0.4 MV/cm),

Fowler–Nordheim tunneling regime (E > 0.4 MV/cm),

where J is the current density, E is the applied electric field, m* is the effective mass of electrons, and φ_B is the junction barrier height. The schematic energy band diagrams for both direct and F–N tunneling conductions are illustrated in Figs. 6(c) and 6(d), respectively. Direct tunneling shows a linear relationship with the applied field E and exponential dependence with insulator thickness d as shown in Eq. (1). Hence, this tunneling mechanism is dominant in thinner oxide films at low voltage.²⁰ On the other hand, F–N tunneling occurs when the applied electric field is large enough to cause electron wave functions to tunnel through the triangular potential barrier profile in the insulator layer,²¹ as shown in the energy band diagram in Fig. 6(d). This is consistent with fabricated FTJ current-voltage conduction mechanism characteristics shown in Fig. 6(b), in which FTJ devices exhibited F–N tunneling for E > 0.4 MV/cm. Calculated R² values of 0.995 and 0.998 were found for direct tunneling and F-N tunneling, respectively. The discussed conduction mechanism analysis validates that dominant on state current transport mechanisms for fabricated TiN/Al₂O₃/HZO/TiN FTJ devices are tunneling conductions, i.e., direct tunneling at low electric field and F–N tunneling at high electric field.

Endurance and retention characteristics of these Al₂O₃/HZO based FTJ devices were studied to qualify reliability of our devices. Figure 7(a) shows the remanent polarization in ferroelectric film with a number of switching cycles. The ferroelectric HZO film showed a significant wake-up effect up to ∼5 × 10⁴ switching cycles yielding a maximum remanent polarization value of ∼13 μC/cm² at 3.75 V pulse amplitude and 10 kHz pulse frequency. The observed wake-up effect with the Al₂O₃ layer FTJ device is most likely due to homogeneous distribution of defects with continuous cycling in ferroelectric layer resulting in an increase in the number of switchable domains and consequently remanent polarization value.²² With more field cycling, the devices showed fatigue behavior in which remanent polarization decreases with switching cycle, shown in Fig. 7(a). The polarization fatigue in the ferroelectric film could be attributed to eventual pinning of switching domains by generated defects in ferroelectric layer with continuous field cycling.^22,23 The FTJ current density evolution with endurance cycles was analyzed for both MIM stacks (with and without Al₂O₃ layer), shown in Fig. 7(b). The bilayer FTJ stack showed significant improvement in device endurance behavior, with maximum endurance limit extending up to 10⁶ switching cycles. The Al₂O₃ layer facilitates tunneling for up-polarization state and acts as a barrier layer in down-polarization state, as explained in the energy band diagram schematic in Fig. 5(a). Hence, an increase in on-state current density and a decrease in off-state current density were observed with bilayer FTJ stack, Fig. 7(b). An increase in both on- and off-state current density with endurance cycles is most likely due to an overall increase in device leakage current originating from defects/trap states generation in ferroelectric layer.¹³ In FTJ retention measurement, shown in Fig. 7(c), a gradual drift in on-current was observed resulting in reduction of TER ratio with time. A residual TER ratio of ∼2.1 was extracted after extrapolation to 10 years in data retention characteristics. The drift in current values could be attributed to depolarization field caused by incomplete charge compensation at Al₂O₃/HZO interface.²⁴ 

In order to optimize FTJ devices with respect to both TER ratio and maximum endurance cycles (N_c), we investigated their dependence on write pulse width and amplitude. Figure 8(a) shows the FTJ TER ratio with pulse width (100 ns–10 ms) for a wide range of write pulse amplitude (1–4 V) values. An increase in write voltage amplitude/pulse width enhances ferroelectric polarization in HZO layer resulting in an increase in the TER ratio. The slope of TER increase reduces at higher write voltage amplitude/pulse width (3 V/100 μs) due to an increase in off-state leakage current density. When the device was stressed at 4 V amplitude with 1 ms pulse width, the large magnitude of leakage current through the device causes hard breakdown in oxide layer diminishing the TER effect in ferroelectric tunnel junctions. Unlike TER, maximum endurance cycles N_c shows an inverse relationship with write pulse amplitude/time [Fig. 8(b)]. High voltage/time stress induces the generation of interface and bulk defects in the dielectric increasing overall leakage current and consequently limiting FTJ endurance performance.¹⁶ Maximum N_c of ∼3 × 10⁶ was observed for the lowest applied write amplitude (2 V) and pulse width (100 ns) at the cost of a low TER ratio. Hence, a clear trade-off between TER ratio and endurance limit could be observed in fabricated bilayer FTJ devices, enforcing the need of suitable programming parameters for optimal device performance.

To improve storage density of ferroelectric tunnel junction memory, the FTJ devices were also investigated for MLC functionality. The observed phenomena of an increase in remanent polarization in ferroelectric layer and a consequent increase in FTJ tunneling current with V_WRITE amplitude was used to demonstrate MLC behavior in fabricated FTJ cells. Five different on-current levels were achieved through write voltage amplitude modulation from 1.5 to 3.75 V, shown in Fig. 9(a). Figure 9(b) shows cumulative distribution of on-current density values measured for different V_WRITE amplitudes. The MLC behavior in FTJ devices can be elucidated using a simplified model²⁵ in which total current density is made up of two different current components: contribution from up-polarization ferroelectric domains and contribution from down-polarization ferroelectric domains, represented by Eq. (5),

where S is the fraction of ferroelectric domains switched with up-polarization state. With an increase in V_WRITE, the S value increases as more fractions of ferroelectric domains can be switched with up orientation and, hence, increases total on-current density. With intermediate write voltage amplitudes, multiple S values can be obtained, and consequently multiple on-current levels can be achieved. It can be observed from Figs. 9(a) and 9(b) that the cycle-to-cycle variation in on-current density is higher at lower V_WRITE amplitudes causing an overlap between on-current levels for V_WRITE of 1.5 and 2 V. This is quantified in Fig. 9(c), where we plotted mean and relative spread (σ_J/J) in on-current density values with different write voltage amplitudes. The mean on-current μ_J decreases from 0.095 to 0.015 A/cm² (>6× reduction) and relative cycle-to-cycle spread σ_J/J value increases from 0.03 to 0.3 (10× increase) when V_WRITE was decreased from 3.75 to 1.5 V. The larger on-current variation at lower write voltage values could also be explained by understanding switching kinetics of ferroelectric domains. When V_WRITE is closer to coercive voltage, the polarization state switching of domains in ferroelectric films is known to be a stochastic and nondeterministic process,²⁶ in which some ferroelectric domains can switch with up orientation while other domains remain in down-polarization state, hence introducing cycle-to-cycle stochasticity in FTJ metrics. This switching variation gets significantly reduced at higher pulse amplitudes when most of the ferroelectric domains have already switched into up-polarization state.²⁷ 

For a comprehensive statistical analysis of device performance, we measured a total of 415 FTJ devices distributed across full 300 mm wafer and the wafer map for TER ratio is plotted in Fig. 10(a). Excluding the edge regions where the TER is lowered by higher leakage current, FTJ devices showed an impressive 4.5–6 TER ratio on center and surrounding regions of the wafer. A full wafer distribution curve is shown in Fig. 10(b). The full wafer mean and standard deviation of measured TER ratios for 415 FTJ devices was found to be 4.96 and 1.2, respectively. We also investigated intradie and interdie variations in FTJ switching, plotted in Fig. 10(c). The raw data points for the box plots are also shown. The intradie variation is found to be much higher as compared to interdie variation likely due to variation in HZO/Al₂O₃ interface properties, which significantly impacts the device TER ratio.

Table I tabulates statistics for FTJ performance metrics analyzed for center region and full wafer devices. The full wafer and center region analysis is carried over 415 and 125 FTJ devices, respectively. The TER ratio increases from full wafer mean value 4.96–5.38 for center region devices. We also demonstrate an impressive switching yield of >80% based on characterization of FTJ devices on the center region of the wafer. The switching yield is defined by FTJ cells exhibiting a TER ratio of >2. In addition, the variability in FTJ switching was also investigated across full wafer. We report low cycle-to-cycle (0.25) and cell-to-cell variability (0.83) in the FTJ TER ratio for center region devices. Expectedly, the TER variability increased in full wafer statistics when relatively higher leakage edge region devices were included in the statistics. Further studies are planned to explore the thickness and characteristics of the ferroelectric film and tunneling barrier, to optimize the TER, reduce variability, and achieve high endurance.

We successfully implemented CMOS-compatible Zr doped HfO₂ based nanoscale (100 × 100 nm²) ferroelectric tunnel junction devices on 300 mm wafer platform. We demonstrated that separating ferroelectric layer HZO and tunneling layer Al₂O₃ could significantly improve FTJ performance over conventional TiN/HZO/TiN based FTJ structure. The modified FTJ device stack (TiN/Al₂O₃/HZO/TiN) demonstrated an excellent TER ratio of ∼5 and endurance up to 10⁶ switching cycles. Investigation of current transport mechanism showed that the current in these FTJ devices is dominated by DT at low electric field (E < 0.4 MV/cm) and by Fowler–Nordheim (F–N) tunneling at high electric field (E > 0.4 MV/cm). Further improvement of TER and endurance will require enhancing the asymmetry of the tunneling barrier created for the two polarization orientations and optimization of film thickness for the ferroelectric and tunneling layers. Write voltage amplitude modulation based MLC operation yielded four distinct current levels resulting in improved storage density of FTJ devices. The FTJ devices were optimized with respect to write voltage amplitude and pulse width and low cycle-to-cycle and cell-to-cell variability along with impressive switching yield (∼80%) were accomplished across full 300 mm wafer. The development of high-performance and high-yield CMOS-compatible nanoscale FTJ devices on a 300 mm wafer platform demonstrates the promising potential of commercially viable industrial adoption of FTJ devices for various NVM based data storage and other embedded memory applications.

The funding for this research is provided by Semiconductor Research Corporation (SRC) under No. SRC/GRC 2825.001 and Air Force Research Laboratory (AFRL) under No. FA8750-19-1-0014. The authors would like to acknowledge the contribution of Tokyo Electron (TEL), North America who deposited the HZO films used in this study and Thermofisher Scientific for assisting with TEM characterization of FTJ devices.

The authors have no conflicts to disclose.

Maximilian Liehr: Conceptualization (lead); Data curation (equal); Formal analysis (equal); Writing – original draft (lead); Writing – review & editing (lead). Jubin Hazra: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Writing – original draft (equal). Karsten Beckmann: Conceptualization (equal); Investigation (equal). Vineetha Mukundan: Investigation (equal). Ioannis Alexandrou: Investigation (equal). Timothy Yeow: Investigation (equal). Joseph Race: Investigation (equal). Kandabara Tapily: Investigation (equal). Steven Consiglio: Investigation (equal). Santosh K. Kurinec: Conceptualization (equal); Investigation (equal); Project administration (equal). Alain C. Diebold: Investigation (equal). Nathaniel Cady: Conceptualization (equal); Investigation (equal); Project administration (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.