Multiple material stack grayscale patterning using electron-beam lithography and a single plasma etching step

In this last decade, grayscale lithography has been studied^1–3 to pattern 3D structures for micro-optical,³ MEMS,⁴ and other applications. This technique can generate arbitrary shapes with height gradients in the resist profile. The resist profiles are often required to be transferred into an underlying material and it is usually done by deep reactive ion etching (DRIE). For grayscale lithography, material-to-resist etches selectivity, the in-process etch rate variations and the etch isotropy required careful calibration to get the proper profile transferred material.⁵ These aspects have been widely studied to transfer the 3D resist profile using photolithography^6–8 as well as electron-beam lithography (EBL).^9,10 The transfer is usually performed in a single bulk material, meaning that only one material-to-resist etching selectivity is to be considered. The DRIE recipe is rather tuned to reach a 1:1 selectivity to obtain the same profile in the resist as in the material after etching^7,11 or applied a height shrink factor in the resist profile to obtain the desired profile after pattern transferring.^6,10 In a case where the underlying materials are made of multiple materials with different etch rates and selectivity, it will be extremely difficult to calibrate the required resist profile with this approach. Other approaches have been developed to create the 3D structure by DRIE in a multiple material stack for nanoscale devices like hybrid photolithography and EBL for carbon nanotubes field effect transistors¹² or nanoimprint lithography to create thin-film transistors,^13,14 but different etching steps were used with the selective etching rate to transfer the 3D resist profile in the different material etch. In this paper, we present an empirical method to calibrate the etching transfer after grayscale EBL in a multilayer stack using a single plasma etching step to fabricate 3D structure for nanoscale devices.

The proposed method is used to fabricate an array of TiOx resistive memory cylinder junctions on top of an Al bottom electrode for the fabrication of resistive memory crossbars. Resistive random-access memories (ReRAMs) can be integrated into crossbar array architecture to process vector-by-matrix multiplication in the analog domain. These passive crossbars are made of two sets of electrode arrays, bottom electrodes (BEs) and top electrodes (TEs), perpendicular to each other with a resistive memory at the intersection of each BE and TE as shown in Fig. 1. Passive crossbar circuit fabrication process reported in the literature pattern the active memory stack in the same step as the TEs fabrication^15–19 as illustrated in Fig. 1(a). Meaning that the memory stack is standing below the TE even when it is not needed. In Fig. 1(b), we propose an alternative architecture where the memory stack is patterned as a cylinder shape at the intersection of the BEs and TEs. Studies show that decreasing the memory area can increase the resistance ratio and decrease the power consumption.^20,21

The process flow is illustrated in Fig. 2. The BE and the memory pillars are etched using grayscale lithography and a single plasma etching step. A dielectric layer is then deposited and planarized by chemical-mechanical polishing (CMP) to reveal the memory pillars. Finally, the TE is patterned by plasma etching.

This study focuses on the fabrication of the BE and the memory pillars as shown in Fig. 2. We will show that it can be made in a single etching step. It has the advantage to decrease the number of fabrication steps; moreover, the memory pillar and the BE will be self-aligned. The stack used is composed of seven different layers made of four different materials with a thickness between 200 and 10 nm but the proposed method can be applied on any multimaterial stack. The height resolution achieved in the transferred profile is in the order of the tenth nanometers.

Grayscale lithography is used to create 3D shapes with height gradients, enabling the fabrication of textured surfaces with nanotopographies.¹ As shown in Fig. 3(a), the resist can be exposed at different doses resulting in a specific resist height after development. The relationship between the dose and the remaining height is called the contrast curve (CC), illustrated in Fig. 3(d) for a negative resist. If the targeted shape in the resist is a grayscale image noted $T(x,y)$⁠, where $T$ is the target height depending on the lateral coordinate $x,y$⁠, the applied ebeam doses $D$ is

The resist structure needs to be transferred into the underlying materials for the targeted application by DRIE. The etching recipe can be adjusted to get a selectivity between the resist and the material equal to 1:1. In this case, oxygen is added to the plasma as it is known to increase the resist etch rate until obtaining the same etch rate in the material^7,9,11 resulting in the same resist and material profile. If the selectivity is not 1:1, the topography will be affected and the height shrink factor is applied to get the desired shape after transfer.^6,10 As an example, for a pyramid shape with a specific resist slope, the slope transfer by plasma etching in a bulk material will have an angle increase or decrease depending on the selectivity. To create the desired topography, the effect of the angle needs to be considered. If $S$ is the selectivity between the resist and the material, the applied dose for the target shape will be

When the transfer is done on multiple materials stacked on each other with different etch rates, the resulting shape can become complex and difficult to control as shown in Figs. 3(b) and 3(c). For a specific etching recipe, the final shape will depend not only on the etching rate of the resist and all the different materials etched but also on the thickness of each layer and the etching time. The model to determine the applied dose presented above could be adapted if all the parameters are known individually but will be strongly dependent on their accuracy. Moreover, chemical diffusion at the interface of each material can increase the complexity of the etching rate evolution over the multilayer stack. The applied dose required to get the targeted shape after the transfer can be challenging to obtain. A complex sequence of different etching steps with specific selectivity could be used as in Refs. 13 and 14. In Sec. II, a method to calibrate the transfer using a unique etching step for the full process will be presented.

We propose a method to calibrate the dose required to get a specific shape after plasma etching in a multilayer stack without knowing precisely the thickness and the etch rates of the different materials in the stack. To measure a CC, large squares, larger than the 3$β$ value, are patterned at different doses. The remaining thickness after the development is then measured for each square, resulting in a curve describing the relationship with the remaining height vs the applied dose [see Fig. 3(d)]. The dose range can be determined with the CC and usually correspond to the remaining thickness between $25%$ and $75%$ of the starting resist thickness.

The test is repeated in this dose range with a higher number of points for better accuracy and a more precise CC and the resist patterned structures are etched by plasma etching. The structures are measured after resist striping and an etching calibration curve (ECC) is determined as shown in Fig. 4. The ECC will, therefore, describe the relationship between the remaining height in the multilayer stack after the plasma etching and the ebeam doses. The ECC can be used to etch a targeted shape in the stack. The applied dose will be

for a target structure defined by $T(x,y)$⁠. This ECC has the advantage to be simple and fast to measure and requires only one sample will the full stack. The only information needed is an estimation of the time required to etch the full stack.

This study will use the method to fabricate restive memory on BEs with a stack made of Al, Ti, TiOx, and TiN material, but the procedure is valid for any arbitrary stack as long as an etching recipe, which can etch all the material, is used. For example, it could be used to fabricate thin-film transistors as published in^13,14 but with grayscale lithography and a unique etching step. For this application, a negative resist is used for exposure time consideration but the method remains valid with a positive resist; the only requirement is a low contrast resist. In that case, the ECC will decrease with the dose rather than increase.

This section presents the fabrication of BEs and memory pillars of a resistive memory crossbar array in a single step with the architecture presented Fig. 1(b). As shown in Fig. 2(a), the stack deposited for the BEs and pillars fabrication is as follows: Ti/Al/Ti/TiN/TiOx/Ti/TiN (10/200/10/30/30/10/30 nm).

To measure the corresponding ECC of this process, large squares of $200×200μm$ are exposed at 100 keV in the EBL negative resist ma-N 2405 (390 nm thick after spin coating) in a range of doses between 0 and 400 $μC/cm2$ and with a higher number of doses point between 80 and 140 $μC/cm2$ on the full stack. The remaining resist after the development is measured for each dose with a Dektak 150 profilometer to get the associated CC as shown in Fig. 5(a). The sample is then etched using an STS—Multiplex Inductively Coupled Plasma (ICP), with a pressure of 5 mTorr, a gas flux of Cl$2$⁠: 10 SCCM, BCl$3$⁠: 10 SCCM, Ar: 10 SCCM, a coil power of 500 W, a platen power of 50 W, and a temperature of 20 $°$C during 4 min 30 s to etch the full stack, plus a slight overetching of 20 nm when no resist remains after the development. After the etching of the sample test, the ECC is measured with a profilometer.

Figure 5(b) shows the ECC for this process. Since on the dose range studied the relationship between the dose and the remaining thickness of the resist is almost linear, the slope of the ECC can be considered proportional to the selectivity between the resist and the material (supposing that the etching rate of the resist is constant for every dose). It shows that the resist has a low selectivity with the TiN and TiOx layer (highlighted in yellow and red, respectively) and the selectivity with the Al layer is higher (highlighted in blue). It also shows that for some layers like the top TiN layer and the aluminum layer, the etching rate varies over the junction for the same materials. It could come from diffusion between layers or oxidation after the deposition of these materials that change the etching rate behaviors.

As shown in Fig. 5(c), the targeted structure is formed of rectangular BEs composed only of metallic layers (Ti, Al, and TiN) and circular pillars on top, composed of the full stack with the metallic oxide (TiOx) layers. The ECC shown in Fig. 5(b) indicates that the stack starts to be etched when the resist is exposed below 130 $μC/cm2$⁠. Since the pillar should not be etched at all, a dose above 130 $μC/cm2$ is required but for process stability consideration, the resist is exposed at 400 $μC/cm2$⁠. It corresponds to the dose where the resist has no solubility with the developer to get the full resist thickness and protect the pillar from the etching during the full process. The BEs area needs to be partially exposed to stop the etching in the TiN layers between the memory (TiOx layer) and the BE (Al layers). This means that for the BE area, the remaining thickness after the etching needs to be between 210 and 250 nm. The targeted thickness is 230 nm which corresponds, based on the ECC, to an applied dose of 98 $μC/cm2$ for this process.

The target for the BE is to stop in the layers between Al and TiOx. Since the process window is $±20nm$⁠, which corresponds to a variation of $±6μC/cm2$⁠, the accuracy of the ECC measurement needs to be at least $20nm$⁠. From the CC, the resist height after the development can be determined (here 280 nm) for the BE area. This can be useful to monitor the process quality after the development, an AFM measurement can be performed to check before the etching if the BE has the right thickness. It also gives the tolerance of thickness variation. For this process, a variation of $±30nm$ in the resist after the development can be accepted.

Figure 6 shows SEM images of the BE with memory pillars on top, patterned in the resist after the development (a) and after etching and resist striping (b). Figure 6(c) shows a FIB cross section of the structure. The zoomed SEM images show the aluminum BE with a width of 1.5 m and the TiO resistive memory patterned in a pillar shape with a width of 250 nm. The SEM images show that the BE was partially etched with a remaining thickness of 220 nm. Figure 6(c) was taken after the full process fabrication. A dielectric layer was deposited on the 3D structure and planarized by CMP. Only the memory pillars were revealed and the BE is encapsulated in the dielectric layer. The TE was then patterned.

This result shows that grayscale lithography can be used to shape nanoscale devices by plasma etching with gradient height shape in a single ebeam exposition followed by a single plasma etching step. With the proposed method, a height control of around 10 nm is achieved with a multistack layer composed of seven layers with thicknesses in the tenth of nanometers.

The ECC depends on the resist, resist thickness, the composition of the stack, etching rates, and thickness of the different materials used. As shown in Fig. 5, the process window is small. The ECC can drift due to shelf-life, a drift of the CC, a variation in the etching plasma process, and development time variation. In that case, the applied dose will not result in the expected height after the etching. For those reasons, the calibration curve should be monitored from time to time to correct process drift and control process stability.

The stability of the process can be improved by increasing the process windows. It is well established²² that using a low-contrast developer improves process control in grayscale lithography. Since the slope of the CC will be lower, the remaining thickness will be less sensitive to dose variation. In the same way, decreasing the etching selectivity between the resist and the material used will decrease the slope of the ECC and makes the process less sensitive to dose variation. The etching recipe can be, therefore, adapted to decrease the etching rate of the material to decrease selectivity.

The quality of the process will be strongly affected by the proximity effect correction used. For this process, a module of the beamer software from GenISys GmbH specially made for grayscale lithography is used. The module corrects the applied dose to compensate the backscatter signal. Nevertheless, the short- and mid-range effects were not corrected and can sometimes lead to failures, especially when the height gradient is steep.

Negative resists are crosslinked during exposure, the more the resist is exposed, the more it is crosslinked and, therefore, the development rate decrease. A partially exposed resist will have lower mechanical stability and will be more sensitive to adhesion issues. ma-N 2400 has low adhesion and this limits the minimum dimension of the BE that is partially exposed. It was observed that below 1 m width BE, the structures takeoff. A solution is to increase the development time to shift the contrast curve on the right and increase the applied dose required. Therefore, the effective dose absorbed for the same remaining thickness in the resist will be higher and get better resistance to adhesion but will increase the exposure time. An alternative solution could be to change the resist for another EBL negative resist Medusa 82 that has better adhesion than ma-N 2400 and has shown grayscale capability.²³ 

In this study, a method to calibrate the transfer by plasma-etching of grayscale ebeam lithography on multistack layers was presented. The method needs the same test structures used to measure contrast curves. Large squares exposed at different doses are etched and the remaining thickness is measured to get the ECC that describes the remaining materials thickness after the etching process as a function of the dose. The applied dose can, therefore, be determined with this curve to etch the targeted profile in a full stack. It was shown that this method can be used for nanoscale devices.

With this method, a novel ReRAM crossbar architecture with metallic BEs and pillar shape oxide-based ReRAM on top was fabricated. The dimension achieved was 1.5 m width for the BE and 250 nm diameters for the memory pillars. The partial etching of the BE could be stopped in the 30 nm TiN layer between the electrode and the memory with a height resolution of 10 nm. The proposed method can be extended to any application requiring grayscale topography on multilayers material at the nanoscale level.

The limitation and challenges of this process were discussed. The use of ma-N 2400 negative resist limits the critical dimension of the BE. The process is mainly sensitive to the resist shelf-life and the etching recipe reproducibility. Careful monitoring of the ECC should be considered.

This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC) HIDATA project (No. 506289-2017) and Mitacs Accelerate program (No. IT19472).

The authors have no conflicts to disclose.

R. Dawant: Conceptualization (lead); Data curation (lead). S. Ecoffey: Supervision (equal); Validation (equal). D. Drouin: Resources (equal); Supervision (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.