Designing MoS₂ channel properties for analog memory in neuromorphic applications

Besides the replacement of silicon in CMOS-like logic applications¹ and scaling of transistors up to sub-10 nm gate length,^2–4 2D materials offer a possibility to realize alternative post-CMOS solutions^5,6 for the development of semiconductor devices. Driven by the needs of the electronics industry and new approaches such as neuromorphic engineering,⁷ the need for analog memory is on the rise. Neuromorphic computing is another approach to intelligent machines based on the non-von Neumann architecture, where such memory is in great demand due to the possibility of performing analog or hybrid (analog/digital) operations.

Non-von Neumann analog memory cells can be realized using a memristive effect observed in 2D materials due to point defects.⁸ Hysteresis observed in memristors based on 2D materials is also associated with several sources: adsorbates on the channel surface, grain boundaries in the channel volume, defects on the channel/oxide interface, mobile ions in oxides, and defects close to the substrate/oxide interface.⁹ Another option is the application of 2D materials scaling capabilities in nonvolatile random access memory (NVRAM) based on charge trapping in the oxide layer.¹⁰ Such memory provides some advantages over CMOS-RAM cells, which show a much greater size in comparison with NVRAMs because six transistors are required to operate CMOS-RAMs. 2D channel materials allow one to achieve better conductance modulation using the space charge, providing the required voltage shift of the transfer characteristics of FETs.

Currently, the question of how to design the channel properties and the operation conditions to tune the memory state numbers and the linearity is not fully addressed. In the present work, how channel thickness and carrier concentration allow to tune the memory state distribution and that pulse width modulation is able to improve the linearity of the conductance response curve of the NVRAM memory cell will be shown.

Figure 1 demonstrates the schematic representation of the device structure used in simulation. A charge-trapping stack is composed of $MoS2/Al2O3/HfO2/Al2O3$⁠, where $Al2O3$ acts both as a tunnel and a barrier oxide, $HfO2$ serves as a charge-trapping layer, and ultrathin-$MoS2$ is a channel material, which provides carriers to the trapping layer. The top gate is used for FET channel modulation, while the bottom gate controls the write and read processes. The bottom gate material is TaN.

A schematic illustration of the charge-trapping process under depression conditions is shown in Fig. 2(a). When positive voltage is applied to the bottom gate, carriers from the channel are tunneled into the charge-trapping layer through the thin $Al2O3$ layer. Then, tunneled carriers are trapped by the $HfO2$ defect states. The space charge formed by trapped electrons influences the carrier moving in the channel causing the reduction of channel conductance.

If a negative voltage is applied between the bottom gate and source contacts [Fig. 2(b)], holes from $MoS2$ are forced to tunnel into the $HfO2$ layer. Then, they recombine with trapped electrons, causing the reduction of space charge. The conductivity of the channel is restored to its initial value.

Channel and gate stack oxide material properties are given in Table I. It was supposed that material properties of multilayer MoS$2$ (between one and six layers thick) including carrier mobility in the channel are in linear dependence on the number of layers according to Ref. 11. The device dimensions, as well as trap parameters, are presented in Table II.

comsol multiphysics was used as a simulation package. The model combines a 1D study of Fowler–Nordheim (FN) tunneling current through the charge-trapping stack, which is further used in 1D time-dependent simulations of trapped charge density in $HfO2$⁠, and a 2D study of FET transfer characteristics. As soon as the current model considers only depression conditions, when electrons are tunneled into the charge-trapping layer, the equations will be given only for electron fluxes. The tunneling current expression shown in Ref. 17 by Fowler and Nordheim in terms of the Sommerfield model was extended using the WKB approximation¹⁸ and takes the form

where $JFN$ is the Fowler–Nordheim tunneling current, $Eins$ is the electric field in the insulator, and $AFN$ and $BFN$ are Fowler–Nordheim coefficients, which can be calculated by the following formulas:

where $q$ is the electron charge, $mMoS2∗$ is the effective mass of electrons in $MoS2$⁠, $mox∗$ is the effective mass of electrons in the tunneling oxide layer (⁠$Al2O3$⁠), $ΦB$ is the barrier height, and $h$ is Planck’s constant.

Simulated FN tunneling current with calculated coefficients $AFN=1.93×10−6A/V2$ and $BFN=6.83×108$ V/m is used for time-dependent simulation of trap occupancy distribution. A 2D stationary model of FET operating at depression conditions is based on the obtained trapped charge distribution. Hereby, channel conductance versus pulse number is calculated from FET transfer characteristics. For 1D simulation of charge trapping in the $HfO2$ layer, several charge fluxes in and out of the trapping layer are determined in the model and demonstrated in Fig. 3.

Obtained results from 1D simulations are implemented in the two-dimensional stationary model, which describes the behavior of the FET structure. This model is based on drift-diffusion equations. To include the effect of quantum confinement in the device physics simulation, the density-gradient formulation was used to include a contribution from the gradients of the concentrations to the equations of states via quantum potentials.

The space charge density accumulated in the $HfO2$ layer charge causes screening of the electrons moving in the channel. This affects the reduction of channel conductance, which can be calculated from the transfer characteristics of the device.

Simulated FN tunneling current density through the charge-trapping stack is given in Fig. 4. According to Ref. 10, the operating bottom gate voltage was chosen to be 6 V. This value allows to precisely control the accumulated charge in $HfO2$-layer voltage by application to the bottom gate voltage pulses with 50 ms duration. Lower values of voltage pulse amplitude require a much longer duration of pulses, whereas higher voltage amplitude values do not allow to control the amount of charge with the required accuracy, reduce the device reliability, and can lead to breakdown.

The FN tunneling current decreases for thicker channel materials. The reason for this is the observable modest difference in the channel properties for different number of $MoS2$ layers. However, at the same time, a thicker channel material has higher carrier mobility, which is strongly reduced by the vertical electrical field from the gate. As soon as the channel conductance is largely determined by the carrier mobility, for a thicker $MoS2$ channel, the initial conductance will be higher. This opens up opportunities for improving the device performance by increasing the number of available memory states due to the enlarged difference in conductance between the initial and the most depressed state of NVRAMs.

The operating cycle of the NVRAM consists of “write” and “read” parts. During the “write” process, the device is in depression conditions when the voltage pulses are applied between the bottom gate and the source and the charge is accumulated in the $HfO2$ layer. To “read” data from the device, the voltage is applied between the drain and the source. The top gate is used to tune the potential barrier in the $MoS2$ channel and control the output current. The resulting channel conduction obtained from the device carries information about the current state of NVRAMs.

The “write” process of NVRAMs is described quantitatively by the trap occupancy. This is a parameter whose value ranges from 0 (all states are fully unoccupied) to 1 (all states are occupied). The dependency of trap occupancy distribution from applied voltage pulse duration is given in Fig. 5.

Starting at a certain pulse duration, trap occupancy saturation is observed. Accumulated negative charge causes reduction of tunneling current, which imposes a limitation of maximum space charge density in $HfO2$⁠. Thus, further increasing the thickness of the $HfO2$ layer will not allow one to increase the number of available states of the device by further suppressing the conductivity of the channel due to the growing space charge from trapped electrons. As the trap levels are filled, the channel conductance decreases until it reaches saturation.

“Read” process is described by the 2D model of the FET structure. Simulated transfer characteristics of the NVRAM are shown in Fig. 6. The reduction of the channel conductance caused by the charge in the $HfO2$ layer results in decreased drain current density with each voltage pulse applied to the bottom gate [Fig. 6(a)], which corresponds to the depression conditions of the device operation.

Figure 6(b) demonstrates potentiation conditions, when the trapped electrons recombine, decreasing the space charge. The conductance of the channel is recovered up to the initial value. The model does not consider any effects related to the oxide degradation after many operation cycles. Hence, the channel conductance state of an NVRAM cell is reset without any hysteresis in the simulation.

The results indicate good agreement with the experiment from Ref. 10 in the subthreshold region with almost identical subthreshold swing. However, there is a noticeable difference in the saturation region. The deviation reason is relatively high gate contact resistance due to the low contact area, which is usually observed in practice and was not taken into account in the model. That means saturation observed in the model corresponds to the situation with ideal metal top gate contact. In addition, during the development of the model, it was considered that we have an ohmic contact to the source and the drain. In practice, the realization of such conditions for scaled devices and monolayer materials could be challenging.

Based on the obtained data, the channel conductance response curve is calculated and is shown in Fig. 7. The application of voltage pulses with constant amplitude and width leads to the high nonlinearity (⁠$σ$⁠) of memory states distribution. To quantify the nonlinearity, the mean squared error formula can be used,

where $N$ is the pulse number, $gDS$ is the actual state conductance, and $g^DS$ is the predicted value, which corresponds to a linear relationship between the maximum and minimum states of the channel conductivity.

It could be noticed that the effect from the first and last voltage pulses on the channel conductance is negligible. To improve the conductance response curve linearity, it is required to apply pulse width modulation as demonstrated in Fig. 7: the first pulse was set to 75 ms with a subsequent reduction to 71 ms in 0.1 ms steps. This impacts in a reduction of nonlinearity for 1 order of magnitude, which highly improves the device performance for neuromorphic calculations. The number of observed states is increased from 32 up to 40.

The average difference in conductance between two adjacent memory states shows the response of memory states distribution caused by the accumulation of the same amount of space charge. Higher values mean that the device could be operated using shorter voltage pulses, which improves the performance of the NVRAM. That value is affected by different material and device parameters. Among them, we can distinguish such parameters as channel doping and channel thickness. These parameters could be relatively easily controlled to enhance the available number of memory states. The simulated dependence of the average difference in conductance between two adjacent memory states on the $MoS2$ channel doping and thickness is given in Fig. 8.

Higher difference in conductance between adjacent memory states is observed with an increasing number of layers. The same correlation is observed for channel doping. Up to a certain value, the difference between two memory states is increasing with increasing dopant concentration, as soon as more free carriers are provided by the doping. From a certain concentration, doping difference between two memory states starts to decrease. The reason is the reduction of space charge influence on increased amount of free carriers in the channel.

In summary, we have presented a model of a NVRAM cell for a full write/read cycle. Transfer characteristics were simulated and memory state distribution was calculated. It is shown that linearity and the observed number of states could be increased by the application of the pulse width modulation. The impact of channel parameters on memory state distribution was studied. Linear increase of average difference in conductance between memory states with an increasing number of channel layers is observed. This allows us to achieve more memory states with the same operational conditions. The optimal value of channel doping is $1012cm−2$⁠.

It is worth noting that the device operates for a rather long time (up to 1 s for the “write” process), but this is a reasonable value for nonvolatile charge-trapping devices as the main advantage of such devices is the long period of data storage and high packing density. This makes NVRAMs indispensable for neuromorphic applications including the ability to perform analog operations.

The work was supported by the Carl Zeiss Foundation within the framework of the MemWerk® project, Contract No. P2018-01-002.

The authors have no conflicts to disclose.

The data that support the findings of this study are available from the corresponding author upon reasonable request.