Hybrid cross correlation and line-scan alignment strategy for CMOS chips electron-beam lithography processing Open Access

Back-end-of-line (BEOL) integration of microelectronic devices above CMOS integrated circuits (ICs) has attracted much attention in the last decade either to increase device density or add functionality. Demonstrations have already been shown for in-memory computing applications,¹ quantum computing,² and integrated nanophotonics.³ Electron-beam lithography (EBL) is a powerful platform for R&D and prototyping that provides design and layout flexibility together with the high-resolution capability for emerging technology development. In this paper, we will discuss the challenges in terms of EBL alignment on top of ICs at the node 130 nm and below and present an alignment procedure based on cross correlation.

Different methods exist for EBL alignment. The classical method, which we will refer to as line-scan alignment, consists of a scanning square marker or cross. The electron beam scans the area where the marker is supposed to be along vertical and horizontal lines. The backscattered electron detected signal is used to locate the edges of the shape and calculate the coordinate of the marker center.⁴ Another known method for EBL alignment^5,6 is based on a cross-correlation algorithm of two images. The full area of the marker location is scanned by the electron beam, and the shift between the marker in the backscattered electron images and the reference image from the pattern file is extracted. The shift between the scanned image and the reference image is measured by a phase correlation algorithm. A Fourier transform is applied to both images, and the cross-power spectrum between the Fourier transform is computed. By applying the inverse Fourier transform of the cross-power spectrum, the shift between the two images can be determined.

The line-scan method is commonly used for its simple implementation, speed, and precision below 5  nm.⁷ It is limited by the quality of the marker edges and requires a large clear space around the marker to avoid signal disturbance during marker scanning. Different factors can impact the quality of alignments, such as the material contrast between the substrate and the marker or the marker depth.⁴ The alignment performance can be improved by scanning the mark repeatedly and averaging the result of each line-scan.⁸ For the cross-correlation alignment, the marker design is a critical factor that affects the accuracy of the overlay alignment.^9,10 It is more time-consuming compared to the line-scan approach due to the requirement to scan the whole marker area. The beam step size will also affect the accuracy even though it has been shown that subpixel accuracy is achievable.¹¹ This technique is useful when the marker is partially damaged, and sub-5 nm alignment can be reached even with up to 80% of the marker pattern missing.⁵ 

BEOL materials, more specifically thick dielectrics, and design rules are fixed for each CMOS technology node and represent challenges for both the EBL of nanostructures and the alignment with the last metal level patterns for further postprocessing. Cu damascene, which first appeared at the 130 nm CMOS node, forced the use of dummy structures that do lead to design rules specific to each CMOS node that were introduced afterward.¹² These rules impede minimal and maximal dimensions as well as minimal and maximal spacing, usually around a few micrometers and about a tenth of micrometers for minimal and maximal dimensions. As shown in Fig. 1, the maximal spacing does not allow the drawing of a large clear space around the marks to perform an alignment by line-scans.

To address this issue, cross correlation is a strategy that can be exploited for the EBL alignment on top of CMOS ICs. Multiple studies have reported^5,6,13 that Penrose tiles are good candidates for correlation-based alignment due to their aperiodic properties. Penrose tilings cannot be implemented on CMOS ICs due to the design rule that only allows specific angled edges (orthogonal and $45°$⁠). For this reason, different types of markers, compatible with CMOS ICs, are proposed and their performance in terms of processing and overlay accuracy will be detailed. We will use a method to quantify the accuracy of the alignment process with an overlay of two lithography levels and present an alignment strategy based on a hybrid method using cross-correlation and line-scan alignment to address the challenges of CMOS IC alignment.

To measure the alignment performance, the overlay test structures shown in Fig. 2(a) are used. The design layers 1 and 2 (EBL 1 and EBL 2) are exposed independently with an alignment before each exposure in a single resist layer. The procedure is the following: a negative resist (MaN 2410), 100 nm thick, is spun on the sample and loaded in the EBPG5200 EBL system. The first alignment by cross correlation is performed, and EBL 1 is exposed in the resist. The sample is unloaded from the tool and reloaded to simulate a real microfabrication process where the wafer position will be shift and misaligned in comparison with the previous lithography step. A second alignment by cross correlation is performed and EBL 2 is exposed. Both exposures were performed at 100 keV, with a dose of 400 $μC/cm2$⁠, a current of 5 nA, and a beam step size of 5 nm. The resist is then developed 2 min with an MF319 solution and observed with a Raith150 Two SEM, after the deposition of a thin Au/Pt layer of a few nanometers, to avoid charging effects.

The offsets between the EBL exposure are extracted by ProSEM software from GenISys. The relative position of every feature is obtained in each quadrant, and X and Y offsets of the two EBL exposures are calculated by the software automatically from the SEM images [see Fig. 2(b)]. The exposure is performed using a 1 mm write field.

The figure of merit used to qualify the alignment is the mean distance-to-center defined as

where $ΔX$ and $ΔY$ are the offset in X and Y and $N$ the number of tests.

Two sets of experiments were performed. The first set on Si substrates is to test the alignment performance of different types of markers. The second set was done on a CMOS die to evaluate the best alignment conditions on CMOS. Every test was repeated 25 times in the same conditions. Figure 3(a) shows the layout of the full sample used for the experiment on Si, 25 chips with different markers on each were used, and the overlay test was exposed inside the chip. As shown in Fig. 3(b), a single chip of $1×1cm2$ was used for the CMOS test.

Three different types of markers were tested on a Si wafer by cross correlation and compared with the classical line-scan alignment method, and the same test was performed with this technique. The markers are made of 80 nm thick W directly sputtered on an Si substrate. They were exposed by EBL and transferred to the W layer by a Plasma Etcher STS Multiplex Inductively Coupled Plasma with the following recipe: $O2$⁠: 5 sccm, $SF6$⁠: 65 sccm, temperature: $20°$C, pressure: 10 mTorr, coil power: 500 W, and platen power: 30 W. The three types of markers shown on top of Fig. 4 are a cross, a QRCode, and a periodic marker known as a Sierpinski carpet. Each marker is 65 $×$ 65 $μ$m$2$ large. The pixel size used by the algorithm for the alignment is 50 nm.

On CMOS TSMC 130 nm IC samples, a marker similar to the Sierpinski carpet shown in Fig. 4 was tested in different configurations. The markers are part of the last BEOL metal level (M8). These are made of 2 $μ$m thick copper and capped by a 900 nm thick layer of SiN. The first test was performed in the same conditions as the markers on Si, i.e., 65 $×$ 65 $μ$m$2$ large and with a pixel size of 50 nm.

The alignment results for each marker tested on Si are shown in Fig. 4. The QRcode shows the best $DTC¯$ of all markers tested by cross correlation with 6.50 nm [Fig. 4(c)]. The cross marker with a $DTC¯$ of 8.23 nm also shows a good accuracy but with lower precision than the QRcode markers [Fig. 4(b)]; i.e., there is a shift from the target position. Finally, the Sierpinski carpet shows the highest mean offset with a $DTC¯=19.57$ nm [Fig. 4(d)]. As shown in Fig. 4(a), the line-scan alignment presents a $DTC¯=1.85$ nm showing that the classical alignment technique should be favored when possible.

The result of the QRCode and the Sierpinski carpet seems to show that the periodicity decreases the precision of the alignment. For correlation-based alignment, the important feature of a marker pattern is the autocorrelation peak of the marker pattern.⁶ The sharpness of the peak will determine the sensitivity to a small positional offset, and thus, a sharper peak will increase the alignment performance. Figure 5 shows the autocorrelation peak of the reference images tested in this study. The sharpness of the peak confirms our experimental results. A sharper peak results in a lower offset.

The best marker design results in an autocorrelation that could be approximated by a 2D $δ$-function. This implies a uniform sampling of frequency space, meaning that the marker should be perfectly aperiodic. For those reasons, it has been shown^5,6 that Penrose tiling¹⁴ is a good candidate for correlation-based alignment due to their aperiodic tiling properties. However, Penrose tiles are not compatible with the design rules imposed by CMOS foundries since a minimum spacing between features is required and only specific angled edges are allowed.

To decrease the peak sharpness of the autocorrelation while remaining compatible with specific design rules, a marker made of an array of structures generated by white noise could be investigated. White noise is a random signal having equal intensity at different frequencies, giving it, therefore, a $δ$-function autocorrelation. Starting from an $n×n$ array of inverted squares, the inner and outer squares can be adjusted following a white noise with a maximum and minimum amplitude set to comply with the dimension and spacing imposed by the design rules. Figure 5 shows that such patterns can drastically increase the autocorrelation peak sharpness and remove the subsidiary peaks around the central peak that are usually present, even in a Penrose tilling pattern.⁶ If the design rule allows it, the pattern can be rotated 45$°$ to exhibit a lack of coherence with the orthogonal pixel array. Small variations in the sampling position will provide significant changes in the detected pattern and, therefore, increase the sensitivity to misalignment.

As shown in Fig. 6(b), the result on CMOS is twice as large as on an Si substrate for a similar marker shape (Sierpinski carpet). This is due to the difference in contrast. The sample on Si has a higher contrast (W/Si) than the CMOS (Cu/SiO$x$⁠). Moreover, the markers on CMOS are capped by a thick layer of SiN that decreases the contrast of the scanned markers. The results on CMOS could be improved with a marker shape that has a sharper autocorrelation peak but will always be worse than on a Si substrate. The alignment can be improved with a hybrid alignment strategy based on first coarse cross-correlation alignment and fine line-scan alignment. As we show in Fig. 1, line-scan alignment is impossible due to the maximum spacing/dimensions. Yet, with a first coarse alignment of 40.79 nm by correlation, it is now possible to target a specific area to perform a line-scan alignment on a small marker square. With this hybrid procedure, we reach a mean offset of 5.2 nm as shown in Fig. 6(c).

Table I summarizes the result performed in this study compared with the literature and their applicability to CMOS IC. The result on an Si substrate shows that for cross-correlation alignment, the marker design impacts the alignment accuracy. Large numbers of edges should be maximized, and periodicity of the marker shape should be avoided. The literature shows that Penrose tilling is the best candidate but cannot be applied to CMOS IC due to design rule limitations. The tests show that line-scan alignment provided a better accuracy compared to the cross correlation of the marker tested in this study but also reported with a Penrose marker,^5,13 although sub-1 nm accuracy could technically be achieved with a Penrose marker.⁶ The hybrid procedure proposed in this work allows benefiting from line-scan accuracy by taking advantage of the cross-correlation method to target a specific area of the marker and perform a successful line-scan even with the design restriction imposed by CMOS technology. This hybrid method is still limited by the quality of the marker inherent to a line-scan procedure. Designing markers with ultralow periodicity and with a sharp autocorrelation peak, compatible with the design rules as shown in Fig. 5, could improve the overlay accuracy.

In this study, we showed a method to test the alignment accuracy of different marker shapes based on a cross-correlation algorithm. The shapes of the markers play an important role in the performance of cross-correlation-based alignment. The alignment accuracy is strongly related to the periodicity of the markers and the number of edges. For good alignment performance, high numbers of edges and aperiodic structures are required.

In this context, the sharpness of the autocorrelation peak could be used as a metric to establish the quality of the markers. We proposed a method based on white noise signals to generate markers constrained by CMOS design rules with ultrasharp autocorrelation peaks.

The result we obtained on CMOS samples led to a mean distance-to-center of 40.79 nm due to the periodicity of the structure but also due to the low contrast of the substrate. This result was improved by using the correlation-based alignment as a coarse alignment, followed by a fine alignment using a line-scan. With this hybrid cross-correlation and line-scan alignment approach, we decreased the $DTC¯$ from 40.79 down to 5.2 nm.

We showed that the cross-correlation alignment can be used on CMOS ICs to workaround the challenges of alignment imposed by the layout design rules. With a hybrid cross-correlation and line-scan alignment, a sub-10 nm overlay accuracy can be achieved.

This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC) HIDATA project (No. 506289-2017) and the Mitacs Accelerate program (No. IT19472).

The data that support the findings of this study are available from the corresponding author upon reasonable request.