Opportunities for ionic liquid/ionogel gating of emerging transistor architectures

Transistors have revolutionized electronic systems for computing, communication, and consumer electronics since the time of their first demonstration by researchers at Bell Labs in the 1940s.¹ They continue to be at the forefront of research as new fabrication methods, materials, and device architectures further improve their performance and new applications are discovered. Recently, researchers have started designing transistors with new three-dimensional (3D) geometries in order to improve computational performance within a given area, and to address challenges of flexibility with conventional transistors for wearable applications.

One approach to realizing transistors with more flexibility and unique, 3D geometries is to utilize an electrolyte gating material, such as an ionic liquid. Ionic liquids are molten salts, at or close to ambient temperatures, which can display high ionic conductivities, wide electrochemical stability windows, and ultralow volatility due to their ion-dense nature. Ionic liquids may also be gelled with a supporting solid network (scaffold) to create ionogels. Ionogel electrolytes enable one to utilize the many favorable properties of ionic liquids in a solid (leakproof) form, and their mechanical properties (e.g., stiffness, stretchability, self-healing nature) can be widely tuned by thoughtful scaffold design.^2–5 Conversely, dielectrics in conventional transistors often exhibit mechanical failure during stretching or flexing, which is not suitable for wearable applications.

A large specific capacitance allows ionogel-gated transistors to operate at lower voltages (typically 1–3 V) and achieve high ON currents, without the cleanroom-based processing techniques necessary to achieve the nanometer-scale thicknesses of conventional dielectric materials for realizing a similarly high capacitance. Thus, ionogels can promote new transistor geometries and substrates that are not amenable to conventional semiconductor fabrication processing. Unlike classical dielectric materials (oxides, polymers), ionogels can be simply and quickly deposited/formed to facilitate all-around electrostatic gating with long-range polarizability, which is of particular benefit in the cases of highly porous semiconductors, 3D device architectures, and nonaligned gate electrodes. Due to the potential for electrochemical doping to occur for certain semiconductor/ionic liquid systems, these devices can also exhibit both electrostatic (non-Faradaic) and electrochemical (Faradaic) behavior, depending on the operating conditions and material choices.^19,21,22 This can lead to significant hysteresis and inconsistencies in device performance. However, when properly accounted for, this can actually be harnessed to promote additional device functionality.²¹ 

Ionogels are uniquely positioned to enable transistors that feature highly porous semiconductor and/or electrode materials, as well as devices that require flexibility and low temperature, straightforward dielectric processing. In this Perspective, we focus on three classes of emerging 3D transistor geometries, depicted schematically in Figs. 1(a)–1(c)], and briefly describe several recent works where ionic liquids/ionogels have either already been employed or may still provide substantial opportunities to improve upon device performance and/or facilitate easier processing. The three emerging transistor architectures are denoted as follows: vertical transistors, where the semiconductor channel is perpendicular to the substrate [Fig. 1(a)]; surround gate transistors, which utilize a suspended or highly porous semiconductor oriented parallel to the substrate [Fig. 1(b)]; and thread or fiber-based transistors, where the substrate has a cylindrical form factor [Fig. 1(c)].

Vertical transistor geometries have been investigated in recent years as an alternative architecture to combat Moore’s Law. Unlike conventional planar transistor geometries, vertical transistors orient the source/drain gap perpendicular to the substrate. This allows one to obtain very small channel lengths, simply by reducing the thickness of the semiconductor, rather than relying on complex optical patterning techniques to achieve nanometer-scale gaps between evaporated electrodes located in the plane of the substrate.^23,24 Reducing the transistor channel length scale is beneficial for device performance in terms of increasing both switching frequencies and saturation currents.²³ Additionally, vertical transistors are promising due to the possibility of increased device density on the substrate by stacking transistors vertically. An in-depth review of vertical transistors was recently performed by Kleemann and co-workers.²³ 

Compared to typical gate dielectric materials, ionogels offer several advantages for the vertical transistor architecture. First, due to the solution-based deposition and tunable rheological properties of ionic liquid-rich ionogels, conformal coating of a porous semiconducting channel material is more attainable by employing an ionogel electrolyte. Ionogels also further improve saturation currents due to the high specific capacitance they provide, in addition to the benefits of the reduced active channel length scale inherent to the vertical device geometry. Moreover, remote gating (gate electrode located to the side, i.e., not aligned with the semiconductor channel) can be enabled due to long-range polarizability of the ion-dense electrolyte.

An example of the successful utilization of an ionogel electrolyte to gate a vertical transistor was reported by Rother et al.²⁵ Semiconducting single-walled carbon nanotubes (SWCNTs) were printed from a toluene dispersion directly onto the source electrode to form the active channel [Figs. 2(a)–2(c)]. The ionogel electrolyte consisted of the ionic liquid 1-ethyl-3-methylimidazolium tris(pentafluoroethyl)trifluorophosphate ([EMIM][FAP]), shown schematically in Fig. 2(d), supported by poly(vinylidene fluoride-co-hexafluoropropylene). Raman spectroscopy confirmed a significantly improved ion penetration utilizing the ionogel electrolyte, as the penetration depth improved from 0.3 μm to over 100 μm.

Baby et al.²⁶ realized printable vertical transistor geometries, which reduced channel lengths significantly (50 nm or lower). This was achieved by printing and annealing an organometallic precursor ink to form a porous SnO₂ semiconductor channel that was vertically stacked between source and drain electrodes. Gating was achieved using a solid polymer electrolyte and remote gating, as shown in Fig. 2(e). While the electrolyte was comprised of LiClO₄ supported by a propylene carbonate-plasticized poly(vinyl alcohol) scaffold, an ionogel would presumably have worked well too. Due to the electrolyte’s ability to conformally coat the highly porous active channel with the electrolyte, the current flow was fully 3D, which allowed the authors to achieve saturation current densities approaching MA/cm² and on/off ratios of 10⁸.

Lenz et al.²⁷ utilized an ionic liquid, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMIM][TFSI]) to modulate the current in an organic semiconductor channel of a diketopyrrolopyrrole-terthiophene donor-acceptor polymer for their vertical transistor design. While maintaining a small footprint and channel length of 40 nm, the authors showed current densities exceeding 3 MA/cm², an on/off ratio of 10⁸, and large transconductances of around 5000 S/m. These values are uniquely high for organic devices and more closely resemble values achieved with SWCNTs or inorganic semiconductors.

Vertical Schottky barrier transistors (v-SBTs) are also of recent interest as a special type of vertical transistor. Briefly, the v-SBT relies on the modulation of the source-semiconductor Schottky barrier height via an applied gate potential. Choi et al.²⁴ demonstrated and characterized a v-SBT that utilized the long-range polarizability of an ionogel electrolyte in order to influence the work function of the source within the vertical stack [Figs. 2(f)–2(i)]. By employing the ionogel in a remote gate configuration, the material requirements for stacking transistors vertically is greatly simplified. In this work, the ionogel consisted of [EMIM][TFSI] supported by a cross-linked polyethylene glycol diacrylate scaffold formed via UV-initiated free radical polymerization, and the authors used Kelvin Probe Force Microscopy to analyze the modulation of the graphene work function with varying gate voltages and distances of the remote gating. When compared to remote gating 30 μm away from the channel using a thin layer of Al₂O₃, the work function of graphene only changed by 0.08 eV at an applied bias of 20 V.

Conversely, for an even farther distance away (50 μm), the work function of graphene could be changed by as much as 1.1 eV when utilizing the ionogel. The authors also demonstrated vertically stacked pentacene and indium gallium zinc oxide (IGZO) v-SBTs [shown schematically in Fig. 2(g)]. The resulting output voltage and signal gain of this device can be seen in Fig. 2(h). The vertical structure enables a drastically simplified device architecture, as it eliminates the need for two separate electrodes and an insulator because of the remote ionogel gating used to modulate the work function of graphene [Fig. 2(i)].

While these works highlight some of the key benefits endowed by ionogel and ionic liquid gating, such as high current densities, low operating voltages, and conformal coatings of porous semiconducting channel networks, there is also a drawback: the slower mobility of ions versus electrons leads to poor switching frequency in electrolyte-gated transistors. Since the vertical transistor design is meant to improve switching frequencies due to shorter channel lengths, this issue needs to be addressed in future studies in order to make ionogel gating a more versatile approach moving forward. Frisbie and co-workers noted in a review that the dissipation factors and DC leakage currents for electrolyte-gated transistors are larger than when one uses more conventional dielectrics, but they also have far larger capacitance values, which can be a significant advantage, depending on the application.²⁸ Nonetheless, electrolyte gating of vertical transistors has enabled printable circuits²⁸ as well as the demonstration of synaptic effects,²⁹ which could be essential for certain applications of this device architecture.

A surround gate transistor geometry facilitates an increase in the semiconductor/gate dielectric interfacial area. This high surface area can greatly increase the total charge density induced in the semiconductor, leading to higher current capacities versus planar transistor analogues. These geometries may utilize an ionic liquid or an ionogel dielectric to ensure conformal contact with a uniquely shaped or highly porous semiconductor. In situ formation of an ionogel (for example, via photopolymerization) is particularly attractive, as a liquid gel precursor solution can first flow through and coat the semiconductor and then be gelled in place to prevent electrolyte leakage.

Franklin et al. demonstrated a top-down fabrication process to realize surround gating of SWCNTs.³⁰ In that study, the authors employed porous anodic alumina as a template to seed and house SWCNTs in each pore (average diameter of 20 nm, with a 100 nm spacing between pores) that were grown via microwave plasma-enhanced chemical vapor deposition. The authors noted that surround gating of SWCNTs using a spin-on glass dielectric facilitated a much shorter screening length, thus decreasing the channel length requirement by 25% versus the planar analogue without encountering short-channel effects. We posit that the performance of these SWCNT transistors could have been further enhanced by the use of an ionogel dielectric, rather than a spin-on glass or ceramic dielectric. Ionogels and ionic liquids are ideal for surround gating geometries, as their tunable rheological properties allow for conformal coating of the semiconductor.

Thiemann et al. utilized an ionic liquid, [EMIM][TFSI], for the uniform surround gating of ZnO nanorods and ZnO nanoparticle films.³¹ The authors noted that without the use of electrolyte gating, the device drain currents were limited to around 100 μA and were not tunable via gate voltage, likely because the conventional SiO₂ dielectric could not conformally coat the ZnO layers efficiently due to the rough nature of the semiconducting films. Conversely, the ionic liquid did achieve a uniform, all-around gating effect to modulate the charge carrier density and thus is ideally suited for applications with similar rough/high surface area semiconductor channels.

In 2015, Wang et al. demonstrated ionic liquid gating of suspended MoS₂ channel transistors for realizing enhanced sheet conductance and coupling efficiencies as high as 4.6 × 10¹³ cm⁻² V⁻¹ [Figs. 3(a)–3(c)].³² This device design allowed for the ionic liquid, dimethyl(2-methoxyethyl)ammonium bis(trifluoromethylsulfonyl)imide, [DEME][TFSI], to conformally coat and seep underneath MoS₂ flakes suspended between titanium/gold source and drain electrodes, as shown schematically in Fig. 3(a) and optically in Fig. 3(b). This suspended channel design doubles the surface area for improved charge density, mobility, and conduction in such 2D semiconductors. Figure 3(c) shows the improvement in sheet conductance obtained by the authors when MoS₂ flakes were suspended and conformably coated by the ionic liquid versus the typical substrate-supported (planar) architecture. It can be seen that the surround gate device structure increased the sheet conductance by 1–2 orders of magnitude versus the conventional planar architecture.

Additionally, ionic liquid gating can be used to induce a charge density in the semiconductor channel that is orders of magnitude higher than by using other gate dielectric materials. Hence, some groups have been able to demonstrate superconductivity in 2D materials by maximizing the ionic liquid/semiconductor surface area. For example, Zheliuk et al. recently utilized the ionic liquid gating of suspended MoS₂ bilayers in order to observe superconductivity in that system.³³ 

A collaboration between our groups in 2016 successfully leveraged ionogel surround gating for 3D graphene foam transistors, achieving high current capacities and low operating voltages.³⁴ We formed the ionogel dielectric by supporting [EMIM][TFSI] with cross-linked poly(pentaerythritol tetraacrylate). Similar to the works previously discussed, pairing the ionogel with a high surface area semiconductor improved current capacity, which was over 26 times higher than that for a similar 2D graphene device. Device transconductance also improved, as the 3D device achieved 22 μS/μm while the 2D analogue achieved only 0.5 μS/μm. Additionally, we also demonstrated that the ionogel gating approach was favorable for flexible electronic applications, as the gel can maintain its dielectric performance while being bent or flexed.

Another example of a surround gate architecture was demonstrated by Liu et al.³⁵ The fabrication approach can be seen schematically in Fig. 3(d). Briefly, the authors utilized an electrospun semiconductor fiber comprised of poly(3,3‴-didodecylquaterthiophene) (PQT-12) and poly(ethylene oxide) that was then ionically gated with a surrounding cross-linked poly(ethylene glycol) diacrylate-supported [EMIM][TFSI] ionogel [shown in Fig. 3(e)]. As the ionogel was created in situ, the precursor solution could wrap almost entirely around the semiconductor fiber before gelation, thus establishing a conformal semiconductor/ionogel dielectric contact. The authors reported a significant increase in the resulting current values of the surround gate transistors versus thin-film devices due to the larger contact area between the semiconductor and ionogel. This device structure was utilized to demonstrate synaptic transistors; the authors claimed that due to the high surface area created by this geometry, the energy consumption per single spike of the synapse was as low as 3.9 fJ.

These works highlight some of the key benefits of utilizing ionic liquid or ionogel gating for surround gate transistor geometries. The gel or liquid can be used to achieve all-around electrostatic gating of a device that is either suspended or has a rough, high surface area nature. The fabrication of these unconventional device geometries can be simplified using ionic dielectrics, as multiple steps are not required to deposit these materials. Further, semiconductor selection does not have to be limited by the need for atomically smooth surfaces in order to realize efficient modulation of charge carrier density.

Thread- or fiber-based transistors have emerged as another alternative device architecture, with the goal of easy integration of computational functionality into wearable devices or smart sutures. While the miniaturization of existing 2D transistor architectures and logic circuits could also accomplish this in principle, researchers have found that utilizing the thread as the substrate itself can offer some distinct advantages. Importantly, the 3D nature of a thread substrate may boost the surface area to volume ratio and improve device performance/sensitivity.

A key challenge for this 3D transistor geometry is obtaining a conformal, uniform layer thickness of a conventional gate dielectric insulating material. Reliable, defect-free dielectrics remain challenging to fabricate on threads, and roughness/uneven thickness of this layer can be detrimental to device performance.^36–38 Using classical microfabrication methods (i.e., lithography, other cleanroom processes) meant for 2D wafer substrates, achieving an all-around coating with a uniform thickness is not straightforward for a 3D fibrous device structure. Many investigators have implemented classical methods to fabricate a transistor on a fiber or wirelike substrate; however, without the use of an ionogel or other electrolyte dielectric, only half of the fiber circumference can be coated via sputtering or evaporation techniques. This leaves a significant portion of the available substrate surface area underutilized. Additionally, in order to create a favorable interface between the semiconductor and a conventional gate dielectric, the fiber typically needs to be coated first with a polymeric material to smoothen the surface.³⁶ 

In 2007, Hamedi et al. first brought electrolyte gating to the thread-based platform when they demonstrated poly(3,4-ethylenedioxythiophene):poly(styrene sulfonic acid) based organic electrochemical transistors (OECTs) on monofilament substrates using a solid polymer electrolyte dielectric.³⁹ The same group also implemented an ionogel gate dielectric using [EMI][TFSI] for a thread-based, poly(3-hexylthiophene) (P3HT) organic field-effect transistor [Figs. 4(a)–4(c)].⁴⁰ They argued that the use of an ionogel helped them achieve this unique geometry due to the forgiveness of small channel misalignments granted by the gel electrolyte. Furthermore, since the capacitance was driven by the formation of an electrostatic double layer, the distance between the gate electrode fiber and the active channel fiber was not as crucial to the overall electronic performance of the device.

Since these pioneering works, several others have also adapted a similar strategy to achieve thread-based transistors. Müller et al. demonstrated silk thread-based OECTs using poly(4-(2,3-dihydrothieno[3,4-b]-[1,4]dioxin-2-yl-methoxy)-1-butanesulfonic acid) and 1-butyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, [BMIM][TFSI].⁴¹ This group achieved an on/off ratio of 10² and was able to demonstrate some washability of their device. While their switching speeds were low, which is common for OECTs, they noted that the unique geometry of thread-based transistors could be used as an advantage over planar OECTs, since a higher surface area to volume ratio would allow for greater contact of the electrolyte to dope/dedope the polymer semiconductor.

Kim et al. proposed a new geometry paradigm for thread-based transistors, which involved a double-stranded assembly of gold source and drain microfibers.⁴²  Figure 4(d) illustrates the difference between this unique double-stranded architecture proposed versus the planar and previously demonstrated thread-based transistors, while Fig. 4(e) shows the device fabrication procedure. With this design, the active channel dimensions are drastically improved, as the width, W, is represented by the length of the fiber strands themselves, and the length, L, is defined by the thicknesses of the semiconductor coatings on the two fiber strands. An ionogel dielectric (polymer-supported [EMIM][TFSI]) was coated around the intertwined source/drain electrodes to provide electronic insulation and ionic coupling to the gate electrode, which was wrapped around the double-stranded assembly. This unique design exhibited on/off ratios above 10⁴, threshold voltages of −0.87 V, and transconductance values of at least 84 μS/mm.

Our groups also recently utilized an ionogel dielectric to achieve electrostatic gating of p-type OFETs constructed on a linen suture thread.⁴³ Our approach notably focused on a cleanroom-free fabrication process [shown schematically in Fig. 4(f)] and employed [EMIM][TFSI] supported by 5 wt. % silica nanoparticles as the ionogel electrolyte. Compared with polymer-supported ionogels, the silica nanoparticle-supported ionogel dielectric was very simple to use in order to realize a conformal coating of the semiconductor, as it did not require any postdeposition curing or cosolvent drying steps. The electrostatic gating achieved via the ionogel dielectric can be seen schematically in Fig. 4(g). We used this ionogel to successfully fabricate both P3HT and SWCNT-based OFETs, with the latter exhibiting significantly less hysteresis. The ionogel-gated SWCNT devices achieved threshold voltages of −0.88 V and on/off ratios above 10².

While ionic liquid/ionogel electrolytes offer significant benefits to thread-based and other 3D transistor geometries, an important consideration of this approach, especially when employing polymeric semiconductors, is the potential for electrochemical doping to occur at large gate biases. This can be mitigated by employing inorganic semiconductors such as SWCNTs or metal oxide semiconductors.⁴³ Regardless, ionogel-gated transistor architectures open unique application pathways to take advantage of 3D substrates and to aid the integration of electronics into textiles and clothing.

Ionic liquids and their solid-supported composites, ionogels, possess several key attributes that can endow 3D transistor architectures with enhanced performance and ease of fabrication. Their deposition at mild (ambient) conditions from either the liquid or viscoelastic gel phase enables cleanroom-free processing of these electrolyte gate dielectric materials. Ionogels can either be formed in situ from a liquid precursor solution, such as via UV-initiated free radical polymerization, or formed first and then deposited, for example, by leveraging the shear-thinning behavior of nanoparticle-supported gels. Ionic liquid/ionogel gating facilitates low transistor operating voltages, typically less than 5 V, and high current densities due to the very large electrostatic double layer capacitance. Remote gating of the semiconductor channel is also an option, owing to the highly polarizable nature of the ionic liquid. The nonvolatility of these ion-dense electrolytes also promotes their extended use without drying out.

As summarized in this Perspective, ionogel or ionic liquid gate dielectrics have already begun to be employed for three classes of emerging 3D transistor architectures, including vertical transistors, surround gate transistors, and thread or fiber-based transistors. The potential for creating highly conformal ionic liquid/semiconductor interfaces using such electrolyte dielectrics is particularly advantageous for both highly porous and 2D semiconductor materials. Both of these semiconductor morphologies have recently begun to be exploited using vertical and surround gate transistors with ionic liquid-based electrolytes. Facile deposition and tunable viscoelastic behavior have both allowed ionogel electrolytes to enable flexible thread/fiber-based transistors as well. It is expected that future studies will further explore the effects of the ionic liquid and/or scaffold chemical identities on ionogel-gated transistor performance.

When optimizing ionic liquid selection for a given transistor application, one will most likely need to consider the details of the semiconductor channel it will be paired with as well. For example, ion size versus pore size in porous semiconductor channels, ionic liquid wettability/contact angle on 2D semiconductor flakes, or potential chemical reactivity with the ionic liquid, to name a few. Despite the fact that sluggish ion motion in ionic liquids, which often have high viscosities, may limit transistor switching speeds, we remain confident that there are certainly practical applications (e.g., wearable sensors) where the low voltage, high current operation, and flexibility offered by ionogel electrolytes can make a substantial future impact. The works that have been summarized here indicate that ionogels can serve as ideal gate dielectric candidates for many new 3D transistor device designs and that many opportunities for these versatile electrolytes still remain.

This work was partially supported by the NSF through an IGERT Grant (No. DGE-1144591), the NSF (Nos. CBET-1935555 and DRL-1931978), and Tufts University.