Study of pit formation in MBE grown GaP on misoriented Si

Silicon (Si)-based multijunction solar cells provide a path forward to achieve high efficiencies at lower costs while utilizing the existing expertise in Si. Traditionally, the solar photovoltaics market has been dominated by silicon technology. The low cost of Si, its ease of fabrication, the extensive knowledge about Si, and its compatibility with other optoelectronic research areas have contributed to its sustained evolution. These factors suggest that the use of an Si bottom cell in tandem configuration is an attractive path to exceed the 32.2% conversion efficiency based on Shockley–Queisser detailed-balance limit for a single junction Si solar cell.¹ Tandem (multijunction) structures comprise of two or more p-n junctions connected to each other. This configuration helps minimize losses due to carrier thermalization to the band edge and nonabsorption of sub-bandgap photons, improving the photon energy utilization and cell efficiency. Numerical simulations have predicted that efficiencies of over 40% can be achieved using material systems of varying bandgaps (1.5–2 eV) as the top cell in a two-junction or three-junction multijunction configuration with Si.² Interest in Si-based multijunction technology has been steadily growing with multiple material systems such as III-V, II-VI, or perovskites being investigated as potential top cell candidates. All the above mentioned material systems have demonstrated the ability to satisfy the bandgap requirements for optimum performance in a tandem configuration.^3–5 III-V material systems such as GaAs and GaP are of particular interest due to the maturity of the technology, ability to achieve long minority-carrier lifetime, and relative structural stability. Integration of III-V materials with Si is a key technological challenge that needs to be addressed for effective cell performance.

Techniques such as mechanical stacking and wafer bonding have been investigated for fabrication of tandem solar cells with III-V (GaAs) top cells and Si bottom cells. Mechanical stacking technology uses the existing expertise in III-V epitaxy and combines it with epitaxial lift-off to enable the reuse of substrates. This particular technology holds the efficiency record for an Si-based multijunction solar cell at 35.9%.⁶ This arrangement allows the cell to operate without current matching restrictions of a series-connected tandem cell. Wafer bonding is a technique where a III-V top cell is bonded to an Si wafer and a bottom cell to create a monolithic multijunction solar cell. Using surface-activated wafer bonding, a conversion efficiency of 34.1% has been achieved for this class of Si-based multijunction solar cells with GaInP and AlGaAs as top and middle cells in the three-junction structure.⁷ Although this technology works well to integrate materials of different lattice constants, it requires a particle free surface and extra polishing steps.

Direct growth of III-V on Si provides an alternative solution with simpler and fewer processing steps, avoiding the need for costly III-V growth substrates, substrate removal, and postgrowth cell integration. Early efforts were mainly focused on GaAs growth directly on Si. However, these growths typically have high defect density due to the large lattice mismatch (4%) between GaAs and Si, impacting minority-carrier recombination in the epitaxial layer.⁸ Additionally, defects associated with the transition from nonpolar Si to polar GaAs and the loss of Si substrate lifetime after growth of GaAs layers are also observed.^9,10 In order to mitigate these effects, a graded buffer layer (GaAs_xP_1 − x) can be introduced between Si and GaAs. This dramatically reduces the density of dislocation loops from 10⁹ cm⁻² to the low 10⁷ cm⁻² range.¹¹ By incorporating these buffer layers, a record efficiency of 24.3% was achieved for an epitaxially grown three-junction GaInP/GaAs/Si solar cell structure.⁷ However, thus far, the efficiency of epitaxially grown III-V/Si multijunction cells lags behind those achieved by mechanical stacking or wafer bonding.

Dilute nitrides are a class of III-V semiconductors with an anomalously high bandgap bowing parameter, such that the addition of small amounts of nitrogen results in substantial reduction in bandgap and changes in electron effective mass.^12,13 The small atomic size of nitrogen enables control over the material's lattice parameter, which can be exploited to grow material that is lattice-matched to Si.¹⁴ However, direct growth of dilute nitride materials on Si is generally not practical due to the formation of SiN_x bonds on the Si surface.¹⁵ To overcome this key obstacle in dilute nitride III-V/Si integration, a common approach is to incorporate a thin GaP buffer layer between Si and the dilute nitride film.

Overall, a GaP buffer layer is key to any potential III-V integration with Si due to its low lattice mismatch with Si: 0.36% at 300 K (based on Vegard's law). Based on this lattice mismatch, the critical thickness for GaP growth on Si is estimated to be about 50 nm.¹⁶ The growth of lattice-mismatched material systems commonly leads to threading dislocations and stacking faults. In addition, the growth of polar material systems on nonpolar substrates frequently shows the formation of antiphase domains (APDs) that can propagate to the surface.^9,17 Toward this end, much work has been devoted to optimizing the growth of GaP on Si. The literature has pointed to the use of (001) Si wafers offcut 4° or 6° in the 〈110〉 direction using migration enhanced epitaxy (MEE) at low growth temperatures to suppress the commonly observed defects in GaP layers grown on Si.¹⁶ Understanding the surface of GaP grown on Si is another critical parameter to achieve high quality dilute nitride materials.

The main focus of this study is to determine deposition conditions that provide effective suppression of pit formation on the GaP surface when grown on Si. Multiple avenues for the formation of pits on the GaP surface during epitaxial growth have been reported in the literature. One potential source of high surface roughness¹⁸ and pit formation¹⁹ are APDs that extend to the surface. The study by Lin et al.¹⁹ optimizes the growth parameters and nucleation sequence and significantly improves the GaP surface and reduce pit formation. The use of intentionally offcut wafers as explained earlier also has the potential to suppress APD's and thereby reduce the associated pit formation.²⁰ Additionally, pit formation has been reported as a result of a phenomenon called melt-back etching during the growth of GaN on Si using the metal organic chemical vapor deposition technique.²¹ This is caused by the etching of Si during the initial GaN buffer layer deposition as a result of high temperature and the presence of Ga nucleation droplets. Subsequent studies on the epitaxial growth of GaP using molecular beam epitaxy (MBE) have also displayed the formation of pits and findings point toward the occurrence of the melt-back etching phenomenon.^22,23 In this work, the effect of using Si substrates with varying orientation was studied with the aim of suppressing pit formation during epitaxial growth.

In order to study the surface quality of GaP grown on Si substrates, epitaxial growth was carried out in a Veeco Gen-III MBE system equipped with In, Ga, and Al effusion cells and As, Sb, and P crackers. Si wafers of three different orientations were used: precise (001) oriented wafers, (001) 4° offcut toward [110], and (001) 6° offcut toward [110]. The Si wafers were cleaned as described by Zhang et al.²⁴ Deoxidation of Si wafers was carried out by annealing at 870 °C for 10 min in the MBE growth chamber. Growth temperature and fluxes were monitored using a thermocouple and a beam flux monitor (BFM), respectively. Surface reconstruction was observed during deoxidization and growth by an in situ reflection high energy electron diffraction system. A high-resolution PANalytical X'Pert MRD x-ray diffractometer (XRD) was used to analyze the structural quality and composition of the MBE grown layers. A Bruker multimode scanning probe atomic force microscope (AFM) was used to examine the surface morphology and determine the root mean square (RMS) surface roughness of grown GaP layers and to identify the presence of pits on GaP and Si surfaces.

The growth of GaP on precise wafers was carried out using the conventional MBE method because there are no reported benefits of using MEE techniques for precise oriented wafers. Post deoxidation, once growth temperatures were reached, the Ga and P shutters were opened. Based on growth optimization, a V/III ratio of 4.6 was chosen. Ga flux of 2.8 × 10⁻⁷ Torr and P flux of 1.3 × 10⁻⁶ Torr, verified using BFM readings, were used.

The growth on 4° offcut and 6° offcut wafers was carried out using the MEE growth technique. This growth technique presents a significant advantage for the suppression of defects such as APDs and stacking faults. The pregrowth cleaning and deoxidation process in this case was similar to conventional MBE growth.

Once growth temperature was reached, the Ga and P shutters were opened in a periodic manner. The cycle starts with 5 s of Ga flux, followed by 10 s pause in order for the Ga to adsorb on the surface. Following this, P flux was provided for 8 s and followed by a 5 s pause. The cycle was repeated until target thickness was achieved. The V/III ratio for MEE growth was maintained at 6. A Ga flux of 8.78 × 10⁻⁸ Torr and a P flux of 5.3 × 10⁻⁷ Torr were used. Postgrowth annealing of GaP layers was also done in P overpressure at elevated temperatures (around 600 °C) for about 10 min. This annealing step was incorporated to improve the surface and material quality of GaP layers. A schematic of the MEE cycle is shown in Fig. 1.

The first set of growths used to study the surface quality and pit formation in GaP grown on Si were carried out on precise (001) oriented Si wafers. Growth temperatures of 580 and 620 °C were used to grow 50 nm GaP layers. For both growth temperatures, Pendellösung fringes present in the double crystal (DC) ω–2θ XRD scans verified the high crystal quality of the grown layers. This also confirmed nondeteriorated vertical coherence of the epitaxial layers (Fig. 2).

Post growth, a surface morphology investigation was performed using AFM. RMS surface roughnesses of 0.698 and 0.735 nm were observed for samples grown at 580 and 620 °C, respectively. Upon examination of the AFM images (Fig. 3), pits were observed as black contours on the surface of GaP layers. The density of pits was around 100 μm⁻² in both the cases. The sample grown at higher temperature demonstrated pits of larger dimension, consistent with literature findings.¹⁹ 

As discussed earlier, the pits can arise from several physical sources, including originating due to the formation of APD's, commonly associated with the growth of GaP (polar material) on Si (nonpolar material). To understand the sources of pit formation and detect the possibility of melt-back etching, GaP layers were chemically removed from the samples using an aqua regia solution (3 HCl:1 HNO₃). Post removal of GaP, an RMS roughness of 0.235 nm was observed for the Si surface with GaP growth at 580 °C and an RMS roughness of 0.246 nm was observed for Si after GaP growth at 620 °C (Fig. 4). The pit density on both the GaP surface before and the Si surface after etching was observed to be around 100 μm⁻². The presence of pits on the Si surface is an indication of melt-back etching, which in addition to APD formation can be contributing to the formation of pits.

The second set of depositions was carried out on (001) Si wafers, intentionally offcut by 4° in the [110] direction. Additionally, these depositions were carried out using the MEE growth technique described in Sec. II. GaP growth temperatures of 360, 400, 440, and 480 °C were used based on growth quality optimization. DC ω–2θ curve, measured by high-resolution x-ray diffraction (HR-XRD), demonstrated lower GaP peak for samples grown at 360 and 480 °C as compared to the 400 and 440 °C growths. Also, the extended interference fringes were of better quality in the 400 and 440 °C cases, demonstrating higher vertical coherence (Fig. 5).

AFM imaging of the GaP surface revealed that the samples grown at 360 and 480 °C had a surface roughness of 0.995 and 0.851 nm, respectively. These samples had pit densities in the range of 50 μm⁻², similar to the GaP grown on precise (001) Si wafers. The GaP grown at 400 and 440 °C had a surface roughness of 0.804 and 0.709 nm, respectively. The pit density for these cases was observed to be substantially lower, in the range of 10–20 μm⁻² (Fig. 6).

The GaP layers were once again removed by chemical etching, and AFM imaging was done on the Si surface. The surface roughness of Si for the samples grown at 360 and 480 °C was 0.276 and 0.235 nm, respectively, with the pit density in the range of 100 μm⁻². However, for the 400 and 440 °C samples, the surface roughness was reduced to 0.206 and 0.193 nm. The pit density observed in the 400 and 440 °C case was around 10 μm⁻² (Fig. 7).

Based on these results, the growth temperature range demonstrating optimum bulk epitaxial layer and surface properties was identified to be at 400–440 °C. We were able to accomplish a tenfold reduction in the pit density due to improved nucleation behavior of the epitaxial layer and a potential reduction in APD formation, associated with the use of offcut wafers.

The final set of growths was carried out on (001) Si wafers, 6° offcut in the [110] direction. It was hypothesized that this substrate orientation would provide two advantages. In addition to reduction in APDs, these substrates would have shorter terrace lengths on the Si surface, thus contributing to more nucleation sites. The presence of more nucleation sites would reduce the Ga flux per nucleation site, as the overall Ga flux during growth is kept constant. Successful depositions were carried out at substrate temperatures of 440 and 480 °C. Growths at lower temperature were 3D in nature and hence are not presented in this work. Examination of DC ω–2θ curves from HR-XRD measurements indicated good crystalline quality of GaP based on the extended interference fringes observed (Fig. 8).

The GaP surface grown using this substrate orientation at 440 °C exhibited the lowest RMS roughness observed in the study of 0.569 nm. Additionally, no pits were observed in a 1 × 1 μm² AFM scan. The pits resurfaced at a growth temperature of 480 °C, and the surface roughness for this case was 0.704 nm (Fig. 9).

On examining the Si surface after the removal of the GaP layer, the sample grown at 440 °C did not have any pits in a 1 × 1 μm² scan, whereas pits were observed on samples grown at the higher temperature of 480 °C (Fig. 10). The Si surface roughness of the sample grown at 440 °C was 0.13 nm and 0.15 nm for the 480 °C sample. Thus, the suppression of pit formation on GaP and Si surfaces was accomplished by using the (001) Si substrate that is intentionally offcut by 6° in the [110] direction.

Growth of a defect-free, high epitaxial quality, and smooth GaP on Si is key to III-V on Si integration. In the initial growths, pit formation on the GaP surface when grown on the Si substrate was observed. The use of three different substrate orientations, namely, precise, 4° offcut, and 6° offcut, revealed that the terrace formation due to the offcut nature of the substrate has an impact on the formation of pits, as summarized in Tables I and II. It was observed that the pit density reduced as the offcut angle of substrate increased. The use of such offcut wafers can help in suppressing APDs due to the bistep formation on the Si surface. The suppression of APDs would lead to the annihilation of the surface pits associated with them. In addition, an increase in the number of step edges on the Si surface can be expected with an increasing offcut angle, resulting in a reduced Ga flux per nucleation site. Thus, the higher offcut substrates are expected to exhibit a lower melt-back etch rate of Si during the Ga nucleation step. Based on the observations of pits in the silicon substrates after removal of the GaP layer and the correlation of the pit densities before and after GaP layer removal, this phenomenon is also a likely contributing factor to the observed reduction in the pit density besides the reductions in APD density. Growth of GaP on the 6° offcut Si substrate at 440 °C demonstrated the suppression of pits on both the GaP and the underlying Si surface. This work presents a key development toward achieving high bulk and surface quality of dilute nitride layers grown on Si for multijunction solar cell applications, forming the basis for further investigation on the growth of dilute nitrides on silicon.

This work was primarily supported by the Engineering Research Center (ERC) Program of the National Science Foundation (NSF) and the Office of Energy Efficiency and Renewable Energy of the Department of Energy (DOE) under NSF Cooperative Agreement No. EEC-1041895. The authors acknowledge the use of facilities within the Eyring Materials Center at Arizona State University supported in part by No. NHCI-ECCS-1542160.