Highly uniform silicon field emitter arrays fabricated using a trilevel resist process

Cold cathodes based on field emitter arrays (FEAs) have shown potential in a variety of commercial and defense applications such as e-beam lithography, x rays, and THz sources.^1–3 However, they have not been able to fulfill the current, current density, and lifetime requirements necessary for these applications. One of the main problems limiting the performance and lifetime of FEAs is emitter tip burnout due to Joule heating, thermal runaway, or cathodic arcs. The problem partially arises from the fabrication process of FEAs, which results in a lognormal distribution of emitter tip radii.⁴ Because of enhanced field factors, the sharp emitters produce excessive current and burnout prematurely, while the dull emitters produce less current and are underutilized. This limits the maximum performance and lifetime obtainable by the FEA.

Previous solutions to reducing tip burnout have focused on limiting the current through the field emitter tips with a current source in order to obtain more uniform emission current. Examples of solutions include placing ballast resistance layers or MOSFETs in series with the field emitter tips.⁵ However, both of these solutions come with some drawbacks. Resistive layers require large resistance values for uniform emission current, which significantly reduce the current performance. Current sources based on MOSFETs are able to provide the high output resistance values necessary to achieve high emission current uniformity without sacrificing current performance. However, MOSFETs occupy a large lateral area, which reduces the packing density of the FEA.

A better solution for reducing tip burnout is to fabricate vertical current limiters directly underneath the field emitter tips. This method is advantageous because it does not decrease the packing density of the array. Recent work by Guerrera and Akinwande⁶ demonstrated the use of vertical nanowires as a means to individually regulate the current through each field emitter tip. These silicon FEAs with vertical silicon nanowire current limiters and self-aligned gate apertures were able to achieve high packing density (10⁸ tips/cm²), high current density (100 A/cm²), and long lifetime (⁠$>$100 h). In this work, we build on the earlier effort by Guerrera and Akinwande to develop silicon FEAs with the goal of further reducing tip burnout. We investigate the effect of the tip radius dispersion on tip burnout, and we focus on improving the uniformity of emitter tip radii (i.e., reducing the tip radius dispersion) as an additional means to mitigate tip burnout.

An important figure of merit to quantify the effect of the tip radius dispersion is the current sensitivity, $S$⁠, which is defined as the emission current variation divided by the mean emission current,⁷ 

As discussed earlier, the current variation within an FEA is due to the tip radius distribution, which often leads to tip burnout. Therefore, reducing the current sensitivity should reduce the probability of tip burnout. One method to calculate the current variation due to the tip radius distribution is to use the mean absolute deviation,

where $IE(r)$ is the emission current of a field emitter with tip radius, $r$⁠, and $f(r)$ is the probability density function describing the tip radius distribution. The mean emission current is calculated as follows:

Equations (1)–(3) describe a generalized method for calculating the current sensitivity of an FEA with any current limiting technique or tip radius distribution. For our silicon FEAs, the field emitter tips are in series with individual nanowires, so the current through each component is the same. The current through the field emitter tip and nanowire can be modeled by the Fowler–Nordheim equation and the ungated FET model, respectively,^8,9

where $aFN$ and $bFN$ are the Fowler–Nordheim coefficients, $gLIN$ is the linear conductance, $VA$ is the early voltage (channel length modulation), and $VDSS$ is the drain-to-source saturation voltage for the ungated FETs. The emission current is related to the tip radius by the field factor, $β=k/rn$⁠, and the field factor is included within the definition of the Fowler–Nordheim coefficients, $aFN$ and $bFN$⁠.¹⁰ When the field emitter tip and nanowire are in series, the gate voltage, $VG$⁠, is divided between the two components (⁠$VGE$⁠, $VDS$⁠), and the current through both components can be solved numerically.

One method to visualize the numerical solution to the emission current is to use the load line analysis. Figure 1 shows the load line analysis for a distribution of field emitters with different tip radii that are in series with individual silicon nanowires. The points where the curves intersect are the operating points that satisfy both Eqs. (4) and (5) for a fixed $VG$ bias. The current variation, $ΔIE$⁠, in Fig. 1(a) is approximately the difference in current between the field emitters with tip radii $r1$ and $r3$⁠. Figure 1(b) shows that if the tip radius dispersion is reduced, then the curves for $r1$ and $r3$ move closer to $r2$⁠, and thus the current variation and current sensitivity are reduced.

For our current sensitivity simulations, we use a value of $4.075×106$ nm cm^$−$1 and $0.7417$ for $k$ and $n$⁠, respectively.⁶ In addition, $VDSS=1V$⁠, $gLIN=1×10−6S$⁠, and $VA=100V$⁠, which results in a current limiter with a saturation current of $1×10−6A$ and an output resistance of $1×108Ω$⁠. For the tip radius distribution, we use a lognormal distribution⁴ with a mean tip radius of 5.8 nm and a standard deviation (SD) of 1.8 nm. The standard deviation is then varied in order to determine the effect of the tip radius dispersion on current sensitivity and hence tip burnout.

Figure 2(a) shows the simulated current sensitivity of an FEA with different current limiter output resistances, $rOUT$⁠. For $VG<30V$⁠, the simulation shows that the output resistance has no effect on the current sensitivity. This is because the nanowire current limiter is operating in the linear regime, and the resistance in the linear regime is determined by the linear conductance, $gLIN$⁠, instead of $rOUT$⁠. In terms of tip burnout, the high current sensitivity at low $VG$ is not a problem because the emitters do not reach a high enough current to burnout. For high $VG$⁠, the current sensitivity improves significantly for every $10×$ increase in $rOUT$⁠. However, there is only a small improvement in current sensitivity above 10⁸ $Ω$ and almost no improvement above 10⁹ $Ω$⁠. The optimal output resistance appears to be around 10⁸ $Ω$⁠, and any further increase in $rOUT$ yields decreasing marginal improvement in current sensitivity.

Figure 2(b) shows the simulated current sensitivity of an FEA with different tip radius distributions. For each distribution, the mean tip radius (5.8 nm) is the same, and the tip radius standard deviation, $σ$⁠, is varied. At low $VG$⁠, the current sensitivity decreases significantly with decreasing $σ$⁠. Again, this is because the nanowire is operating in the linear regime where the resistance is lower, and changes in $σ$ have a greater effect on current sensitivity at lower resistances. At high $VG$⁠, there is a small improvement in current sensitivity with each decrease in $σ$⁠; although, there is not much improvement to be made since the current sensitivity is already $<0.05$ due to the nanowire current limiter.

When comparing Figs. 2(a) and 2(b), the curve for $rOUT=108Ω$ in Fig. 2(a) and the curve for $σ=1.8nm$ in Fig. 2(b) are the same. In Fig. 2(b), the curve for $σ=1.5nm$ shows a lower current sensitivity for $VG<67V$ when compared to the curves for 10⁹ and 10¹⁰ $Ω$ in Fig. 2(a). For $VG>67V$⁠, the higher output resistances in Fig. 2(a) have lower current sensitivity, and they are able to achieve a minimum current sensitivity of $S<0.01$⁠. However, the curve for $σ=1.5nm$ in Fig. 2(b) is also able to achieve a minimum current sensitivity of $S<0.05$⁠. These differences in current sensitivity for $VG>67V$ are minor, and therefore a small reduction in $σ$ of 0.3 nm yields better or equivalent current sensitivity to an increase of 2 orders of magnitude in $rOUT$⁠. These simulations show that decreasing the tip radius dispersion is a viable alternative to further increasing the output resistance of a current limiter in order to achieve a similar or better current sensitivity.

The FEAs reported in this work were fabricated on 150 mm diameter, n-type (1–5 $Ω⋅cm$⁠), $⟨100⟩$ orientation, single crystal silicon wafers. The fabrication process for the silicon FEAs is a slightly modified version of the self-aligned, CMP-based process developed by Guerrera and Akinwande.⁶ Figure 3 shows the key process steps in the fabrication of silicon FEAs with vertical nanowire current limiters. For the formation of the silicon tips, the most important steps are (1) photolithography that forms the oxide hard mask (i.e., “dots”) for the silicon tips, (2) isotropic reactive ion etch (RIE) that forms the silicon necks, and (3) oxidation that sharpens the silicon necks into silicon tips. Each of these process steps is nonuniform to some degree, which affects the tip radius dispersion. For instance, Fig. 4 shows a diagram of how the variation in the dot diameter affects the isotropic etch. If the etch is uniform, then any variation in the dot diameter will translate to the neck diameter, and the variation will also propagate to subsequent steps. Ultimately, the variation in the dot diameter contributes to the tip radius dispersion at the end of the fabrication process.

The tip radius distribution is first established during the photolithography step, using an i-line (365 nm) stepper, which patterns the 1 $μm$ pitch arrays of 0.5 $μm$ diameter dots that become the etching mask for the silicon field emitter tips. If the uniformity of this photolithography step is improved, then it should reduce the tip radius dispersion. For the single layer photoresist process used by Guerrera and Akinwande,⁶ the light reflected at the resist/silicon interface is between 40% and 50% (Fig. 5). The reflected light results in interference effects that affect the exposure dose required to clear the resist for different resist thicknesses. This phenomenon is quantified by the “Swing Curve,” which shows the variation in critical dimension (i.e., dot diameter) versus resist thickness for a fixed exposure dose. In order to improve the critical dimension uniformity, the amplitude of the Swing Curve must be reduced. The Swing Curve amplitude is quantified by the Swing Ratio, $S$⁠, which is the difference between adjacent minimum and maximum values of the Swing Curve divided by their average value,¹¹ 

where $R01$ is the reflectance at the air/resist interface, $R12$ is the reflectance at the resist/substrate interface, $α$ is the resist absorption coefficient, and $D$ is the photoresist thickness. One method to reduce the Swing Ratio is to reduce the reflectance, $R12$⁠, at the resist/substrate interface by adding a bottom antireflective coating (BARC) between the resist and the substrate. Figure 5 shows a plot of the calculated reflectance, $R12$⁠, vs BARC thickness for a resist/BARC bilayer stack. The calculation shows that by using BARC, the reflectance can be reduced to $<$0.1%, which would reduce the Swing Ratio by a factor of $50%/0.1%>20$⁠.

One problem with the resist/BARC bilayer stack is that a conventional $O2$ plasma etch will etch both the photoresist and the BARC simultaneously, thereby resulting in an inaccurate transfer of the dot pattern. To remedy this problem, we use a trilevel resist stack consisting of a high-contrast photoresist layer as the top layer, an interlayer dielectric (SiO$2$⁠) with high etch selectivity as the middle layer, and a BARC layer as the bottom layer.¹² Table I gives the refractive index of each material used in the trilevel resist stack. The etch process for this trilevel resist stack consists of two steps: the first RIE with CF$4$ transfers the dot pattern from the resist to the SiO$2$ interlayer, and the second RIE with O$2$ transfers the dot pattern from the SiO$2$ interlayer to the BARC. The advantage of using an interlayer is that the dot pattern in highly selective SiO$2$ is not etched when being transferred to the BARC during RIE with O$2$⁠, and thus the accuracy of the dot diameter is preserved. Figure 5 shows a diagram of our optimized trilevel resist stack with the thickness values required for each layer to achieve a reflectance of $<$0.1%.

In order to test the effectiveness of the trilevel resist, we also patterned the arrays of 0.5 $μm$ photoresist dots using a single layer photoresist process, and we used a scanning electron microscope (SEM) to measure the dot diameters of both processes. For both trilevel resist and single layer resist processes, we imaged 100 dots in a straight line in the center of a $1000×1000$ array. Imaging in the center of a large array removed the likelihood of any edge effects, such as reflections or different diffraction patterns that may occur on the perimeter and penetrate into the array. We repeated this procedure for three different dies for each of the photolithography processes and obtained a total of 600 images. After the images were obtained, a binary threshold filter was used to isolate the dots from the background of the image, and a circle was fitted to the dot image in order to extract the diameter.

Figure 6 shows a histogram of the extracted dot diameters for the trilevel resist and single layer resist. The distributions are nearly symmetrical, and therefore we fitted a normal distribution to the data. The SD of the distributions is 3.7 and 8.8 nm for the trilevel resist and the single layer resist, respectively. The SD of the trilevel resist is 5.1 nm less than the SD of the single layer resist, which represents a 60% reduction in SD. This is strong evidence that using the trilevel resist to eliminate the light reflected at the resist/substrate interface helps increase the uniformity of the dots and hence the etching mask for silicon tips. As discussed previously, a more uniform etching mask should reduce the tip radius dispersion.

We incorporated our trilevel resist stack from Sec. III into the existing silicon FEA fabrication process described by Guerrera and Akinwande.⁶ Figure 7(a) shows the transfer characteristics for several FEAs with different array sizes that were fabricated using a trilevel resist process. For these measurements, the anode voltage, $VA$⁠, was fixed at 3000 V while the gate voltage, $VG$⁠, was swept from 0 to 50 V. In addition, the anode was placed approximately 1 cm above the FEAs. The FEAs are able to operate at $VG>50V$⁠; however, the maximum operating voltage was limited to 50 V in order to allow a fair comparison between different array sizes. Figure 7(b) shows the Fowler–Nordheim (FN) plot associated with Fig. 7(a). Table II lists a summary of important parameters extracted from the transfer characteristics and FN plot in Fig. 7.

For these FEAs, $bFN$ was nearly identical for all array sizes. It is important to note that the FEAs measured in Fig. 7 were all from the same die, which had an area of $7×7$ mm². Given their close proximity and nearly identical $bFN$⁠, this suggests that the field emitter tips are highly uniform. From $bFN$⁠, the field factor, $β$⁠, can be extracted by using the electron affinity of silicon as the work function. In addition, the relationship between the field factor, $β$⁠, and tip radius, $r$⁠, is $β=k/rn$⁠, as discussed previously. Thus, the tip radius can also be extracted from $bFN$⁠. The extracted tip radius for these field emitters is approximately $6.0−6.5nm$⁠, which is consistent with a mean tip radius of 5.6 nm measured using SEM in prior works.⁴ The anode current per tip is nearly the same for large arrays, indicating that the field emitter tips are uniform and scalable. However, a few of the small arrays do not scale as well. During the photolithography process, we observed that the dots on the perimeter of the array were disfigured or deformed. Therefore, it is possible that the field emitters around the perimeter are not working. This perimeter effect has a greater impact on small arrays because the field emitters on the perimeter form a larger percentage of the entire array; thus, the anode current per tip is lower for small arrays. However, the small arrays have nearly the same $bFN$ as large arrays, indicating that the functioning field emitters in both small and large arrays are uniform and scalable.

To highlight the benefits of the trilevel resist fabrication process, we benchmarked the performance of the FEAs presented in this work against other FEAs reported in the literature. The fabrication process for the FEAs in this work and Guerrera’s work^6,13 is almost identical. The key difference is that Guerrera used a single layer photolithography process for the silicon tip formation; all other process steps were identical. It is not fair to compare the maximum current performance in this work with Guerrera’s work because the device parameters reported by Guerrera were extracted at a higher $VG$⁠. Therefore, the current and current density of Guerrera’s FEAs are much higher than the FEAs in this work. However, the $bFN$ values can be compared. In Guerrera’s work, there is large variation in $bFN$ (⁠$503−785V$⁠) between the smallest arrays, namely, the single emitter, $5×5$⁠, and $25×25$⁠. However, $25×25$⁠, $32×32$⁠, and $50×50$ have a $bFN$ of around $450−500V$⁠, similar to the respective FEAs reported in this work. In addition, the $bFN$ values reported by Guerrera for the $100×100$ and $1000×1000$ FEA are 365 and 275 V, respectively. For a fair comparison between similar array sizes, the total $bFN$ range for Guerrera’s FEAs is (⁠$275−503V$⁠) while the total $bFN$ range for the FEAs in this work is (⁠$511−521V$⁠). This narrow range in $bFN$ is a major sign that the FEAs fabricated using a trilevel resist process have more uniform field emitter tips than FEAs fabricated using a single layer photolithography process.

We have shown that reducing the tip radius dispersion is a viable method for achieving FEAs with low current sensitivity and reducing tip burnout. As a result, the value of the output resistance, $rOUT$⁠, of the current limiter should be reconsidered. For future FEA design, it is possible to further increase the aspect ratio of the silicon nanowire in order to increase the output resistance and reduce tip burnout. However, this approach would reduce the maximum current while only marginally improving the current sensitivity and greatly increasing the fabrication complexity. For example,⁴ if a silicon nanowire has a fixed diameter of 100 nm and a donor doping concentration of $5×1014$ cm⁻³, then the output resistance increases from $107$ to $109Ω$ when the channel length increases from 1 to 10 $μ$m. However, the saturation current of the silicon nanowire also decreases from $10−6$ to $10−7$ A. Fabricating silicon nanowires with aspect ratios greater than 50:1 is a significant microfabrication challenge. Instead of increasing the aspect ratio and output resistance, a more uniform FEA fabrication process can be used, such as the trilevel resist process in this work, and the aspect ratio and fabrication complexity of the silicon nanowire could be reduced while still achieving a similar current sensitivity.

Although the FEAs presented in this work were able to achieve uniform $bFN$⁠, they were not able to achieve the current and current density performance anticipated. The results thus far suggest that the fabrication problem is now a yield problem instead of a uniformity problem. During the trilevel resist photolithography step of the fabrication process, we observed that the dots were disfigured or deformed around the perimeter of each array. This is most likely due to the reflections at the abrupt junction between the SiO$2$ shallow trench isolation and silicon mesa where the field emitters are fabricated. For smaller arrays, such as the single emitter, $5×5$⁠, and $10×10$⁠, all of the dots were disfigured, which is most likely why these FEAs did not work at the end of the fabrication process. This effect could possibly be mitigated by using a more advance photolithography process that employs optical proximity correction.¹⁴ 

Improving the uniformity of the photolithography process was a significant step forward in producing more uniform FEAs. However, there are still further steps that affect the distribution of emitter tip radii, and the uniformity of these steps should be improved. These steps include the RIE that forms the silicon necks, the oxidation that sharpens the silicon necks into silicon tips, and the CMP that defines the gate aperture. The RIE and CMP processes are particularly sensitive to pattern densities across the die or the wafer, and uneven features can cause variations in etch rates or polishing rates. For instance, the large spacing between different FEAs in this work can cause the polishing pad to deform in CMP and result in different polishing rates for different FEAs. This can drastically affect the yield of certain array sizes. One proven method to solving this problem in CMOS processing is to insert dummy features that fill any available space between active devices.¹⁵ These dummy features are electrically isolated from circuits and devices, and they reduce the pattern density variation across the wafer, resulting in more uniform RIE and CMP. Subsequent revisions to the FEA fabrication process could leverage this “dummy fill” technology in order to reduce the tip radius dispersion.

In this work, we fabricated silicon FEAs using a trilevel resist process in order to increase the uniformity of emitter tip radii. In order to test the effect of the tip radius dispersion, we simulated the current sensitivity of FEAs with different tip radius distributions and current limiter output resistances. The simulations show that a small decrease in tip radius dispersion of 0.3 nm is equivalent to an increase of 2 orders of magnitude in output resistance. Therefore, decreasing the tip radius dispersion is an effective alternative to further increasing the output resistance. In order to reduce the tip radius dispersion, we use a trilevel resist process to increase the uniformity of the array of dots used as the etching mask for the silicon tips. This process works by eliminating the light reflected at the resist/substrate interface, which causes variations in critical dimension at a fixed exposure dose. Using the trilevel resist, we were able to reduce the standard deviation of the dot diameter by 60% compared to a single layer resist process. Device characterization showed that FEAs with different array sizes have a very narrow $bFN$ range, which indicates that the field emitters within the FEAs are highly uniform.

This material is based upon the work supported by DARPA under Grant No. N66001-16-1-4038. This work was carried out in part through the use of MIT’s Microsystems Technology Laboratories.