Effect of vacuum thermal annealing to encapsulated graphene field effect transistors

Graphene field effect transistors (GFETs) have been of great scientific interest since the isolation of graphene by Novoselov et al. in 2004.¹ Exploiting graphene's unique electronic properties, researchers have been able to build transistors with record high field effect mobilities² and impressive RF performance.^3,4 The stability and reliability of these devices still remains a challenge. Due to the 2D nature of graphene, GFETs are highly susceptible to various chemical adsorbents that exist in the surrounding environment.⁵ Researchers have demonstrated that water and oxygen molecule adsorption is mainly responsible for the increased p-doping and hysteretic behavior of GFETS operating in ambient environments.⁶ 

A variety of encapsulation methods have been proposed to prevent unintentional doping,^7–11 increasing the stability of GFETs while operating in air. In addition, methods such as current annealing,¹² solvent treatment,¹³ thermal annealing,¹⁴ and oxygen plasma cleaning¹⁵ have been widely used to etch or desorb the unwanted dopants from graphene and regain device performance to as-fabricated levels. However, encapsulated GFETs are still prone to the effects of the environment after prolonged air exposure (weeks to months) as oxygen and water molecules can still slowly diffuse through the encapsulation layers. Furthermore, cleaning methods present only a temporary solution, since devices have to be kept under vacuum or at low temperatures, limiting their use in real world applications.

In this work, we combine both encapsulation and thermal annealing techniques to mitigate the effects of the environment, recover the electronic performance of GFETs to as-fabricated values, and examine the question of whether encapsulation layers also trap water inside the device system. Using a low thermal budget encapsulation method that we previously presented,¹⁶ we study the effects of varying vacuum annealing time on encapsulated devices and propose a mechanism of recovery. In addition, by testing nonencapsulated devices in oxygen only (dry air) and an ambient air (O₂/H₂O) environment, we were able to highlight the contribution of each dopant on the Dirac point shift and mobility degradation of GFETs. Our results clearly show that vacuum annealing can further enhance the air stability of encapsulated devices by reversing the effects of dopant diffusion after prolonged periods of air exposure. We believe this is an important result toward the evolution of graphene-based electronic devices.

Back-gated GFETs were fabricated using graphene grown by chemical vapor deposition (CVD) on 20 μm copper foils. Graphene was then transferred on top of p-doped silicon substrates with a 300 nm thermally grown oxide. Our transfer method uses a spin coated (3000 rpm for 45 s) poly(methyl methacrylate) (PMMA) layer along a polydimethylsiloxane (PDMS) stamp as support layers in order to minimize the defects (cracks and wrinkles) during transfer. The PDMS/PMMA/graphene/Cu foil stack is then inserted into an ammonium persulfate bath for 5 h in order to etch the copper, followed by a deionized water rinsing step for 24 h to minimize the chemical doping from the copper etchant. Samples were left to dry in air under a laminar flow hood overnight, while Si/SiO₂ substrates were treated by UV-ozone (10 min) to reduce organic contamination of the SiO₂ surface prior to transfer. Cleaned substrates were annealed at 180 °C on a hotplate for 10 min while the PDMS/PMMA/graphene stack was placed on top for 60 s. Finally, a chloroform bath (2 h) followed by an acetone and isopropyl alcohol (IPA) rinsing step was used to dissolve the PMMA left on top of graphene after transfer.

Drain and source electrodes (3 nm Cr/50 nm Au) were thermally evaporated using a shadow mask. An additional PMMA masking layer was drop cast on the transistor channel in order to protect it from reactive ion etching that was used (20 s at 50 W) to etch unwanted graphene from the rest of the silicon wafer. This step was followed with another bath of chloroform (2 h)/acetone/IPA to dissolve the PMMA. Nonencapsulated (uncapped) devices were immediately inserted into a CVD system to deposit 1.25 μm of parylene-C followed by a 50 nm thermally evaporated aluminum layer on top. Another set of devices was encapsulated with the same method after one week of air exposure.

For the electrical measurements, the devices were placed on a heating plate in a vacuum chamber (20 mTorr) and with the aid of a probe station and pA meter/DC voltage source HP 4140B, the transfer characteristics I_DS-V_GS at V_DS = 50 mV were obtained, either in vacuum environment or in ambient atmosphere for the long-term degradation study. Under the thermal annealing conditions in vacuum environment, two identical devices were examined for each annealing condition: one was electrically measured during the thermal annealing (samples: D1*, D2*, D3*, and D4*) while the other was left in floating potential (samples: D1, D2, D3, and D4). In order to investigate the long term electrical performance, devices were left in ambient environment (20 °C, 40%–50% humidity).

Figure 1 illustrates a schematic of the fabricated nonencapsulated/encapsulated devices. The transistors are bottom gated through the p⁺⁺ silicon.

Figure 2 shows the Dirac point change for the uncapped single layer graphene field effect transistors (SLG-FETs) as a function of annealing time for 390 and 450 K at vacuum. It has to be noted that the transfer characteristics were measured in situ during the annealing. In both annealing conditions, the Dirac point is decreasing with increasing annealing time while the decrease rate along with ΔV_Dirac value depend on the annealing temperature. According to the literature,^5,6 the decrease in Dirac point may be correlated with to the desorption of functional groups, adsorbents, and trapped water molecules between the graphene and the SiO₂.

In order to evaluate the influence of the humidity on the position of Dirac point, the uncapped transistor was subjected to several conditions and the transfer characteristics were monitored, as shown in Fig. 3. Initially, the I_DS-V_GS curve demonstrates a clear p-type behavior with an estimated Dirac point around 50 V and a field effect mobility (μ_FE) of 100 cm²/V s. After 5 h of vacuum annealing at 450 K, the Dirac point shifted toward lower gate voltage values while μ_FE increases by 59% (from 100 to 159 cm²/V s), as seen from the transfer characteristics slope in the left part of the curve. Within the vacuum chamber, dry air was introduced, and the transfer characteristics were monitored after 15 min and 24 h. It is seen that even after 24 h of exposure to dry air, the curve is slightly shifted toward higher gate voltage values as μ_FE stays the same. Finally, the sample was exposed to ambient atmosphere, and after 10 min of exposure, the I_DS-V_GS curve exhibited an abrupt shift toward higher gate voltages. Similarly, 4 h of continuous air exposure of the uncapped device resulted in a positive V_Dirac shift to the direction of the initial (before vacuum thermal annealing) curve with a μ_FE of 113 cm²/V s (28.9% decrease).

Figure 4 illustrates the extracted Dirac point voltage during the conditions mentioned above. Initially, the Dirac point voltage is found at 46 V, and after 5 h of thermal annealing in vacuum, it drops down to less than 20 V. The exposure to dry air has minor effects on the device, as after 24 h, the V_Dirac slightly increases at around 22 V. However, when the GFET is exposed to ambient atmosphere for both 10 min and 4 h, the V_Dirac increases to 26 and 38 V, respectively.

The experiments in dry air and ambient atmosphere clearly show that the transfer characteristics of uncapped GFETs are highly dependent on the humidity that exists in air and a capping layer can be applied in order to provide adequate protection against moisture penetration. The proposed encapsulation method based on a parylene-C and aluminum passivation layer, which offers excellent stability for a long period of time and significantly reduces moisture penetration.¹⁶ To this end, we prepared devices with parylene/Al coating in two different ways: (1) the coating layers were deposited immediately after the manufacturing of the SLG-FET and (2) the coating layers were deposited after leaving the SLG-FET in ambient atmosphere for one week. Our goal was to fabricate devices that have already adsorbed humidity prior to the application of the capping layers.

Figure 5 shows the transfer characteristics of the two types of devices as a function of their exposure time. We observe that the immediately capped device exhibits a near-zero Dirac point voltage, with excellent stability over a period of 1–2 weeks. On the other hand, the devices that have been coated with parylene/Al after the device have been deliberately exposed to air for one week, demonstrate a Dirac point voltage that exceeds 50 V, likely due to humidity adsorption before the capping layer application. However, even for this case, the transfer characteristics of the coated devices are slightly affected by the additional 2 weeks of exposure in air. It may therefore be deduced that the parylene/Al coating presents an excellent protection to both the moisture penetration of the air's humidity and the humidity already adsorbed, if any, by the device. The latter can present some technological limitations on the conditions under which the encapsulation may take place. For instance, if the device has already been exposed to environmental conditions before the application of the capping layers, the system will trap water vapor inside and degradation of the transfer characteristics will be permanent. Hence, it would be of great importance if such devices can be “repaired” after the deposition of the parylene/Al encapsulation. To this end, vacuum annealing at 393 K for various durations was performed to encapsulated transistors.

Figure 6 illustrates V_Dirac as a function of exposure time in air for both immediately capped transistors (D1, D1*) and those that have been capped after one week in air (D2, D2*). Prior to the exposure, the devices have been heated up to 393 K in vacuum for 24 h. In the case of the immediately capped devices, the thermal annealing did not seem to have any particular effect on the Dirac point voltage, as slight modifications from 5 to −5 V were observed after several days of ambient atmosphere exposure. However, when the devices were measured after 30 days of air exposure, the transfer characteristics were degraded so that the V_Dirac was measured at around 30 V and this degradation remained for more than 100 days. An abrupt drop of V_Dirac down to 30 V was observed on devices that were originally degraded after thermal annealing for 24 h at 393 K. In addition, when they were left to air, the decrease of V_Dirac continued, and after 15 days (D2*)/40–50 days (D2), they achieved the lowest value of 9 V (D2) and 32 V (D2*), respectively. When these devices were measured again after 100 days of air exposure, it was found that V_Dirac increased up to 60 V, similar to its initial (before annealing) state. A similar experiment was conducted, where the devices were annealed at the same conditions as before, except that the annealing duration was limited to 3 h. The results are shown in Fig. 7.

We observe that for the immediately capped device D3, V_Dirac exhibits no modification after annealing, even if the device is exposed to air for more than 180 days. On the other hand, immediately capped device D3* that was biased during annealing exhibits an increase of its Dirac point 30 days after the annealing. In the case of capped devices that were exposed for one week, the effect of thermal annealing remains significant, as V_Dirac is reduced from 40 to 17 V. For the next 120 days, D4 device exhibits rather stable behavior with a slight decrease of V_Dirac, whereas device D4* demonstrates a positive Dirac point shift. At this point, it is important to note that, although all four devices follow the same trend, devices D3*, D4* experience a positive V_Dirac shift in contrast to D3, D4.

From the above experiments and observations, we conclude that vacuum annealing of encapsulated devices has an important and continuous impact on the electrical performance of GFETs. It is well documented that parylene-C water diffusivity is relatively low, in the order of 10⁻⁹ cm²/s, and increases almost exponentially with increasing temperature.¹⁷ Our proposed mechanism is that the thermal annealing in vacuum triggers the desorption of water vapor molecules from the graphene surface to the parylene-C film, shifting Dirac point to lower gate values (reduced p-doping). As shown in Figs. 6 and 7, the duration of the annealing plays a crucial role on the lifetime stability of the devices. While GFETs that were subjected to different annealing times show similar initial behavior with a significant reduction in p-doping (negative V_Dirac shift), their long term stability is drastically different. Devices annealed for 24 h (Fig. 6) exhibit an increase in their Dirac point after 20–40 days of annealing, whereas, GFETs annealed for 3 h show no performance degradation for more than 6 months. It is likely that an extended annealing time damages the encapsulation layer, allowing water vapor and oxygen to diffuse from the ambient environment to the graphene surface. Finally, since for the transistors that were biased during annealing, V_Dirac positive shift occurs earlier, it can be assumed that self-heating Joule effect further accelerates the degradation mechanism.

The Dirac point shift, after thermal annealing and during resting at indoor environment, can be approximated by a power time-dependent law of the form V_Dirac = at^b, where t is the duration in days of the device exposure in air after annealing, and a, b are constants. This behavior resembles to standard exponential degradation mechanisms seen in numerous other devices.^18,19

Figure 8 shows the best fits of the previous equation to our experimental data. It has to be noted that the data concerning 24-h device annealing was not included after the 60-day mark. The empirical model fits our experimental data with a constant b value of −0.54 for the 3 h annealed device and −0.74 for the 24 h one.

In summary, increased air stability of GFETs in ambient environments was achieved by employing both encapsulation and vacuum annealing techniques. Our results highlight the importance of annealing time as a successful performance recovery method and emphasize the long-term stability of fabricated devices. A parylene-C damage mechanism is proposed as an explanation to the sudden Dirac point shift on devices subjected to 24 h annealing after prolonged air exposure. We believe that this is an important result for the development of air stable graphene-based electronics.

This material is based upon work supported by the NSF MRSEC program through Columbia in the Center for Precision Assembly of Superstratic and Superatomic Solids (DMR-1420634) and the Defense Threat Reduction Agency (DTRA) under HDTRA1-11-0022.