Tilted ion implantation as a cost-efficient sublithographic patterning technique Free

Scaling of integrated circuit (IC) feature sizes beyond the resolution limit of immersion lithography has been enabled by multiple-patterning techniques.^1–3 However, their significant incremental cost is of concern for further increasing the density of transistors on an IC chip.^2–4 Although so-called next-generation lithography techniques such as extreme ultraviolet lithography, directed self-assembly, and nanoimprint lithography have been extensively investigated, technical challenges hinder their practical application in high-volume manufacturing (HVM).^5–9 Therefore, a more cost-efficient approach is needed to sustain Moore's law.

Tilted ion implantation (TII) recently has been proposed as a cost-efficient technique for defining sublithographic features, as illustrated in Fig. 1.^10–12 By using TII in conjunction with patterned photoresist (PR) and/or hard-mask features formed on the surface of a wafer substrate, sublithographic implanted regions aligned to the PR/hard-mask features can be formed. A substantial difference in etch rates of implanted versus unimplanted regions allows for the implanted regions to be distinguished during a subsequent etch process step, so that the thin masking layer is patterned with sublithographic features. In this paper, the versatility of this technique for forming sublithographic features and pitch-halving is discussed.

Previous work has shown that the etch rate of silicon dioxide (SiO₂) in hydrofluoric acid (HF) solution can be significantly enhanced by ion implantation, if the damage induced is greater than a certain threshold level (e.g., 3 × 10²¹cm⁻³ for SiO₂).¹³ For the purpose of patterning fine features in a SiO₂ masking layer, the layer thickness should be very thin to avoid significant lateral etching during the postimplantation wet etch process. Thus, the effect of TII on the etch rate of ultrathin SiO₂ layers is investigated in this work. Figure 2 plots the measured etch rate in dilute hydrofluoric (DHF) acid solution (200:1 H₂O:HF) for 10 nm-thick thermally grown SiO₂ layers. Ar⁺ implantation was performed at 15° tilt angle, 3.0 keV acceleration energy, and 3 × 10¹⁴cm⁻² dose. Clearly, the etch rate is significantly enhanced, by a factor of ∼9, for the implanted SiO₂ layer versus the unimplanted SiO₂ layer. By comparing the etch rate of the implanted SiO₂ layer against the simulated damage concentration profile obtained using the stopping and range of ions in matter (SRIM) simulation,¹⁴ it can be seen that the etch rate correlates well with structural damage induced by TII.

To demonstrate the applicability of TII for defining nanometer-scale features, spacer lithography³ was used in conjunction with conventional 248 nm deep-ultraviolet (DUV) lithography to form amorphous silicon (a-Si) hard-mask features with sub-100 nm dimensions over a thermally oxidized silicon wafer substrate, as shown in Fig. 3. After the a-Si hard-mask layer was deposited onto the thin thermal SiO₂ layer by low-pressure chemical vapor deposition (LPCVD), a layer of low-temperature-deposited oxide (LTO) was deposited to serve as a hard-mask layer for patterning the a-Si hard-mask layer. Then, a sacrificial layer of a-Si was deposited and patterned by DUV lithography, after which sub-100 nm-wide LTO spacers were formed along the sidewalls of the patterned sacrificial a-Si by conformal deposition (LPCVD) and reactive ion etching (RIE) [Figs. 3(a) and 3(d)]. Next, the sacrificial a-Si features were removed by a selective RIE process [Figs. 3(b) and 3(e)] and then the spacers served as a mask for RIE of the LTO hard-mask layer. Finally, the pattern of the spacers was transferred to the a-Si hard-mask layer with the aid of the LTO hard-mask [Figs. 3(c) and 3(f)].

From Fig. 1, it can be seen that the TII-defined feature size (x) is determined by the implant tilt angle (θ) as well as the mask feature spacing (l), effective height (h), and sidewall angle (α)

Figure 4 shows technology computer-aided design (TCAD) simulations of the implanted Ar profile within the thin SiO₂ masking layer, for different tilt angles. As θ increases from 5° to 25°, x decreases from ∼200 to 100 nm.

Figures 5(a) and 5(b) show experimental results obtained with Ar⁺ implant tilt angles of 15° and 20°, respectively. These samples were subjected to DHF etch followed by RIE of the crystalline silicon (c-Si) substrate, which allows the implanted regions to be easily distinguished. The a-Si hard mask for the sample shown in Fig. 5(a) was not patterned with the aid of a LTO hard-mask layer; therefore, it was etched during the Si RIE process. Taking this into consideration, the angle measured from the edge of the remaining a-Si hard-mask feature to the edge of the etched c-Si region matches the expected value of 15°. In addition, the length of the sub-lithographic feature defined by TII (i.e., x = ∼156.3 nm) corresponds well with the simulation result shown in Fig. 4(a). The sample shown in Fig. 5(b) had a thinner a-Si hard-mask layer which was patterned using a LTO hard-mask. After all of the process steps, ∼24.2 nm-thick LTO remained on top of the a-Si hard-mask features. The angle measured from the edge of the remaining LTO hard-mask feature to the edge of the unetched c-Si region matches the expected value of 20°.

Figure 6 shows a plan-view SEM image of a sample with etched c-Si features defined by 15° TII. It can be seen that these features are self-aligned to the pre-existing a-Si hard-mask features, i.e., the shape of the a-Si hard-mask line edge is reproduced with good fidelity.

Double tilted (positive-angle and negative-angle) Ar⁺ implantation was performed on another sample to demonstrate the feasibility of pitch-halving by TII-enhanced patterning. The implant conditions were the same as for the sample of Fig. 5(a) except that two implants were performed, one at θ = 15° and the other at θ = −15°. Figure 7(a) shows the results obtained for different values of a-Si hard-mask spacing (l). Considering that l is ∼61.4 nm for the leftmost set of a-Si features, the local half-pitch of the etched c-Si is ∼20.5 nm. For the rightmost set of a-Si features with smaller l in Fig. 7(a), there is no feature defined by the 15° implant; this is likely due to asymmetry of the hard-mask spacers, i.e., variations in $h$ and α [cf. Eq. (1)] between the left spacer and the right spacer. Figure 7(b) shows a set of a-Si hard-mask features with much wider spacing so that the implanted regions overlap, i.e., the central region was subjected to double tilted Ar⁺ implantation. The 50 s DHF dip was insufficient to completely remove singly implanted regions of the SiO₂ masking layer [total implanted dose = 3 × 10¹⁴cm⁻² (i)], but sufficient to completely remove the doubly implanted region [total implanted dose = 6 × 10¹⁴cm⁻² (i)]. This is not surprising given that the enhancement in etch rate of SiO₂ is dependent on the amount of structural damage and hence the implant dose.¹³ These results indicate that the TII technique can be used to define various patterns by adjusting the implant dose and masking-layer etch time.

Figure 8 shows that the local density of etched c-Si features is double that of the a-Si hard-mask features. In addition, sub-10 nm (local) half-pitch features are achieved, self-aligned to the a-Si hard-mask features. In short, the TII-enhanced patterning approach can be used to define sub-10 nm features.

TII-enhanced patterning also can be used in conjunction with nonlinear pre-existing masking features on the surface of a wafer substrate. Figure 9 shows results obtained with round hard-mask features (i.e., holes) and a single Ar⁺ implant at 3.0 keV acceleration energy, 3 × 10¹⁴cm⁻² dose, and 15° tilt angle. Figure 9(b) shows a ∼18.6 nm ellipse-shaped etched hole defined by TII. (It should be noted that the shape of the hard mask can be adjusted to achieve a round TII-defined hole.)

TII is demonstrated to be an effective approach for defining sublithographic features and increasing the density of features self-aligned to pre-existing mask features. The TII-defined feature dimensions are controlled by the implant tilt angle, and also depend on the geometrical dimensions of the pre-existing mask features. Using double TII, the density of features can be doubled; local half-pitch as small as ∼9.0 nm was experimentally demonstrated. Because ion implantation is a well-established and relatively low cost process, TII-enhanced patterning can be easily adopted in HVM to help extend Moore's law.

The authors thank Applied Materials, Inc. and Lam Research Corporation for supporting this work. The tilted ion implantation processes were performed by Axcelis Technologies, Inc. The wafers were processed in the Marvell Nanofabrication Laboratory at the University of California, Berkeley. This work was supported in part by the National Science Foundation within the Directorate for Engineering through the Center for Energy Efficient Electronics Science under Award No. 0939514.