ULTRARAMTM is a novel floating-gate nonvolatile memory in which the oxide barrier of flash is replaced by a triple-barrier resonant tunneling structure comprising of multiple InAs/AlSb heterojunctions. The quality of the triple barrier resonant tunneling heterostructure of an ULTRARAMTM device in terms of interface sharpness and the presence of defects was analyzed by cross-sectional scanning tunneling microscopy. We observed two different types of defects: stacking faults originating in the layers below the triple barrier resonant tunneling structure and AlSb accumulations at the interface between the lower AlSb layer of the triple barrier resonant tunneling structure and the InGaAs channel. The InGaAs surface of a second sample was measured by atomic force microscopy in order to investigate whether its unevenness is caused by deposition of the AlSb layer or it is already present before the AlSb deposition process.

A universal memory, long considered the “holy grail” of computing, should combine the best aspects of dynamic random-access memory (DRAM) and flash.1 Fundamentally, such a technology must have very robust logic states that can, nevertheless, be easily changed. As the nature of these requirements appears paradoxical, the widely accepted view is that universal memory is unfeasible1 or almost impossible.2 ULTRARAMTM is a novel, III–V compound semiconductor memory that has demonstrated many impressive properties, which are suggestive of a universal memory candidate, namely, nonvolatility, ultralow switching energy (per unit area)3–5 and fast switching speed with compact architecture (modelled).6 ULTRARAM is a III–V semiconductor floating-gate memory grown by molecular beam epitaxy (MBE) that exploits the InAs/AlSb 2.1 eV conduction band off-set to trap charge.6 A triple barrier resonant tunneling (TBRT) structure contained within the epitaxial crystal, between the channel and the floating gate (FG), is formed by multiple InAs/AlSb heterojunctions, specifically by two InAs quantum wells (QWs) sandwiched between three AlSb barriers. In the absence of a bias, electrons are trapped either in the floating gate or in the channel.7 Electrons are allowed to move across TBRT by the application of a suitable bias ( ± 2.5 V) that causes the QWs’ energy levels to align with the occupied states of the channel (program cycle) or the floating gate (erase cycle).4,8 Detailed information on the ULTRARAM device and how it works can be found in Refs. 4 and 8.

ULTRARAM device performance clearly depends on the TBRT, the channel, and the FG layers. Ideally, these layers should have extremely sharp interfaces and uniform thicknesses at the atomic level. To investigate whether the quality of the grown layers is close to the ideal one, we need a characterization technique able to probe the material with atomic resolution, such as scanning tunneling microscopy (STM).

STM is a powerful technique that allows the imaging of a surface at the atomic level. In particular, cross-sectional scanning tunneling microscopy (X-STM) allows us to analyze the grown layers within a semiconductor material.9 The cross section of a sample can be probed in order to gain significant information on its electronic and structural properties such as interface quality and the presence of defects.

In this work, we present the result of an X-STM analysis on an ULTRARAM sample. The quality of the layers in terms of interfaces sharpness, thickness and composition uniformity was probed, with particular focus on the TBRT structure and adjacent layers, i.e., a 20 nm thick GaSb layer, the In0.8Ga0.2As channel, and the InAs floating gate (Fig. 1). We observed that thin TBRT layers have relatively rough interfaces mostly due to their discrete atomic nature. In addition, the first AlSb barrier (B1) exhibits an unexpectedly irregular thickness due to the presence of top-down triangular shaped AlSb accumulation, which we refer to as nanoridges (NRs), located at the interface with the underlying InGaAs channel. Thus, the channel has an uneven thickness. We also observed the presence of stacking faults originating at the interfaces of the InGaAs channel with the underlying GaSb layer. To investigate a possible mechanism of formation of the NRs, we analyzed by atom force microscopy (AFM) the InGaAs channel top surface of a purposely grown sample. The AFM images also give us further insight into the tri-dimensional shape of the NRs. The relaxation profile of GaSb/InGaAs/TBRT obtained from STM images was reproduced with finite element (FE) simulations based on the continuum elasticity theory in order to investigate whether the InGaAs composition is compatible with the nominal one (group III composition of 80% In and 20% Ga).

In the X-STM experiment, one of the {110} crystallographic planes of the sample is exposed by cleaving it in situ in ultrahigh vacuum and analysed either at nitrogen temperature or room temperature (see Sec. IV). A bias is applied between the sample and an atomically sharp tip, which is scanned over the cleaved surface. The schematic structure of the analyzed ULTRARAM sample A is shown in Fig. 1. Note that one bilayer corresponds to one lattice constant of approximately 6.1 Å. Every layer of the sample was analyzed by X-STM. However, we will focus on the top part of the structure, namely, the 20 nm thick GaSb layer, the InGaAs channel, the TBRT layers, and the InAs FG. The TBRT structure is formed by two InAs quantum wells, QW1 and QW2, respectively, five bilayers (BL) and four BL thick, and three AlSb barriers (B1, B2, and B3). B1 and B3 have an intended thickness of three BL while B2 has an intended thickness of two BL. The target thickness of the In0.8Ga0.2As channel and the InAs FG is, respectively, 20 BL and 16.5 BL. The InAs FG was never completely accessible to our STM analysis due to its proximity to the edge of the cleaved sample. Similarly, complete imaging of the underlying GaSb layer was unfeasible due to the presence of several cleavage-induced step-edges. A large-scale overview of the GaSb/InGaAs/TBRT region is shown in Fig. 2. The various layers, such as GaSb, InGaAs channel, and TBRT layers, can be clearly distinguished from their difference in brightness. The bottom bright layer is the GaSb layer while the following dark layer is the InGaAs channel. The local variation in contrast of the InGaAs layer is due to alloy fluctuation, where Ga-rich areas appear darker and In-rich ones appear brighter. Segregated Sb atoms in the InGaAs layer appear as bright dots. Sb segregation is mostly limited to the first few BL of the InGaAs layer. However, Sb atoms can be observed also in the middle of the InGaAs channel, around 10 BL from the GaSb/InGaAs interface.

Subsequent layers form the TBRT structure. The three bright layers are AlSb barriers (B1–B3) while the darker layers in between barriers are two InAs quantum wells (QW1 and QW2). In Fig. 2, it can be observed that the thickness of B1 is relatively irregular due to the presence of triangular shaped AlSb accumulations at the bottom part of the first AlSb barrier, such as the ones highlighted by the white dashed rectangle in Fig. 2. We refer to these features as nanoridges (NRs) due to their shape. NRs will be discussed with further detail in Secs. II B and II C. The irregularity of the first barrier is reflected in the InGaAs channel that similarly to B1 has an irregular thickness. In contrast, the thickness of the second and third barriers varies only slightly mostly due to the discrete atomic nature of interfaces. Rows of missing atoms can also be observed in Fig. 2, in particular, in the TBRT layers. Despite InAs and AlSb being closely lattice matched ( 1.3 % lattice mismatch), the TBRT layers are nonetheless strained. Therefore, when the sample is cleaved, part of the layers can be ripped out due to the strain. These ripped out regions appear more frequent in our experiments than usual for an X-STM sample due to the presence of defects (see Sec. II B).

The different layers of the structure can be observed in more detail in Fig. 3(a), where next to the X-STM image the schematic structure of the sample is reported. Here, the TBRT layers, with the exception of the first AlSb barrier, have the intended thickness. Again, the different layers can be clearly distinguished from brightness variation. This is not only due to the difference in the material but also due to the relaxation of the cleaved surface.10 In particular, the height profile of GaSb/InGaAs/TBRT [Fig. 3(b)] taken in the STM image in Fig. 3(a) shows that AlSb barriers relax outward further than the the InAs barriers due to the strain induced by the lattice mismatch. Therefore, the AlSb layers appear brighter because they will be closer to the STM tip. Similarly, the InGaAs layer is darker since it relaxes inward. The GaSb/InGaAs/TBRT region was imaged over a relatively wide range of biases at both negative and positive biases, but no voltage dependence was observed and no additional information was gained.

In the height profile, the different layers, i.e, GaSb, InGaAs, the AlSb barriers, the QWs, and the FG, can be distinguished [Fig. 3(b)]. From the profile, it can be seen that the Sb containing layers relax outward while the In(Ga)As layers relax inward, especially the channel. GaSb is taken as reference since the 500 nm GaSb layer (Fig. 1) was grown to be fully relaxed by introducing an interfacial misfit (IMF) array between it and the GaAs substrate5,11 as also as evidenced by the XRD data of Fig. 4. In this way, the strain should be reduced within the first few monolayers from the interface.11 Assuming perfect pseudomorphic growth, the in-plane lattice constant of all layers above the GaAs will be fixed at the GaSb lattice constant. Therefore, the AlSb barriers are compressively strained since AlSb has a bigger lattice constant than GaSb (0.613 55 and 0.609 593 nm, respectively). Contrarily, InAs and In0.8Ga0.2As have smaller lattice constants (0.605 83 and 0.5977 nm) than GaSb; therefore, the In(Ga)As layers are tensile strained.

In order to fit the relaxation profile of GaSb/InGaAs/TBRT, FE simulations based on continuum elasticity theory are performed. One of the aims of simulation is to establish whether relative In and Ga concentrations in the channel of the analyzed sample correspond to the nominal ones, i.e., 80% In and 20% Ga. In Fig. 3(b), the X-STM profile is compared with the curve simulated for a relative In concentration of 80%. It can be seen that the simulated profile deviates slightly from the experimental. However, as we mentioned in Sec. II, the InGaAs layer exhibits alloy fluctuation. Therefore, the In concentration can be either lower or higher than the nominal one in different areas of the sample. Moreover, we observed that the experimental profile varies in different STM images. This is partly due to the electronic contribution to the STM images and to the presence of distinct defects in various STM images. X-ray diffraction (XRD) measurements of the (004) reflection are shown in Fig. 4, along with the results of a simulation to fit the experimental data. An optimal fit is achieved when assuming complete relaxation of the GaSb buffer layer relative to the underlying GaAs, indicating that an IMF array was successfully formed at the GaSb/GaAs interface. The only other layer to show a small 20 % ± 5 % relaxation in the XRD fitting was the 50 nm InAs layer, which is unsurprising as it is above the theoretical critical thickness12 for InAs on GaSb. But for the purposes of the following analysis, it is sufficient to assume that all In(Ga)As and AlSb layers are pseudomorphically strained relative to the GaSb lattice constant.

As previously mentioned, NRs form mostly in the first AlSb barrier at the interface with the InGaAs channel causing both B1 and the InGaAs channel to have an uneven thickness (Fig. 2). Overall, a 2.3  ± 0.2  μm long stretch of the TBRT layers was measured, and 96 NRs were visible with an average separation of 25 ± 4 nm. NRs have either an inverted triangular shape or an inverted trapezoidal shape. The average length of the top side of the NRs is 12  ± 4 nm. The height varies between 3 and 9 BL below the first AlSb barrier including its thickness. The average depth of the NRs is 3.8  ± 0.9 nm (6  ± 1 BL). When the NRs are higher than 6 BL, the formation of NRs was observed also in the AlSb layers B2 and B3. For instance, in Fig. 2, the formation of a smaller NR in B2 stacked above the NP in B1 can be observed (red dashed rectangle). We suggest that the formation of NRs in B2 and B3 is caused by strain-induced nucleation, similarly to the stacking of quantum dots (QDs) first observed by Xie et al.13 Differently, in the case of smaller NRs, B2 and B3 generally show sharp interfaces and a greater constant thickness. This is due to the fact that the formation of a flat surface is energetically favored during deposition.

The NRs result in a locally thicker AlSb barrier. Electrons will have greater difficulty to tunnel through “thick” NRs than through a “thin” AlSb barrier with the expected thickness (three BL). However, at the side of the NRs, the AlSb barriers are typically of the designed thickness or slightly thinner, i.e., two BL or one BL instead of three BL. Electrons with appropriate energy prefer to tunnel through the thinner parts of the barrier at the sides of the NRs. Due to the local variation in the first AlSb barrier and occasionally the first InAs QWs, we expect that local electronic properties of the material will be influenced. However, we anticipate that the device characteristics will not be affected to a significant extent as current will mainly flow through the parts of the TBRT next to the NRs. Reference 8 shows that the TBRT function is quite robust to BL fluctuations in thickness, where B1 is thicker due to an NR.

Moreover, the NRs size (i.e., 12 ± 4 nm) is virtually negligible compared to device dimensions (i.e., 10–20  μm5). Despite the relatively high concentration of NRs, the parts of TBRT with intended layer thickness will be dominant. Thus, we expect the presence of NRs to have little effect on the device characteristics.

A second type of feature that was observed in the ULTRARAM heterostructure is stacking fault. A stacking fault is a planar defect that can form during the growth of a crystal. Stacking faults are caused by an local interruption in the stacking sequence of the atoms.14 For example, in a face-centred cubic (FCC) crystal, the stacking sequence ABCABC becomes ABCBCAB when a ( 111 ) plane is removed from the structure. In this case, an intrinsic stacking fault is formed. Alternatively, an extrinsic stacking fault with ABCBABC stacking sequence forms if an additional ( 111 ) plane is introduced in the crystal structure.15 Examples of stacking faults observed in sample A are shown in Fig. 5(a), highlighted by red dashed rectangles. In Fig. 5(b), an example of thin twins is displayed. A thin twin forms when an intrinsic stacking fault occurs on every ( 111 ) plane of the crystal.15 The formation of a thin twin in the ULTRARAM sample was observed in three different images. The twins we observed in the sample have similar characteristics to stacking faults; therefore, the stacking faults’ description in the next paragraph applies as well to the twins.

The stacking faults originate at the interface between the InGaAs channel and the underlying GaSb layer despite this interface being particularly sharp. The formation of the stacking faults is due to the lattice mismatch between the two materials ( 2.0%). The stacking faults always appear as diagonal features across the layers with an angle of about ± 45 ° with respect to the growth direction. Since we are measuring one of the {110} crystallographic planes, we can establish that the stacking faults run along one of the {111} crystallographic planes. Indeed, as previously mentioned, stacking faults typically form on {111} planes in crystals with an FCC structure, and this is due to the fact that {111} planes have the lowest stacking fault energy.16 

In total, 38 stacking faults with an average distance of 62  ± 14 nm were found. 21 of the stacking faults run along one of the {111} crystallographic planes with a + 45 ° angle while the other 17 have a 45 ° angle. 9 of the stacking faults ends at the bottom of an NR, similarly to the stacking fault in Fig. 5(a) (red dashed rectangle) while the remaining 29 run also through the TBRT layers and terminate at the top surface of the sample. Also in this case, the stacking faults typically correspond to the presence of NRs. However, NRs also form in the absence of a stacking fault. Indeed, the number of NRs (96) is more than twice the number of stacking faults. However, we believe that there is a relation between the stacking faults and the presence of NRs.

Occasionally, a stacking fault favored the ripping off of atoms when the sample was cleaved, as it increases the strain in the structure. In Fig. 5(a), it can be seen that the ripped off part of the layers correspond to the stacking fault highlighted by the orange dashed rectangle. However, regions of ripped off material can be seen throughout the TBRT layers independently from the presence of a stacking fault since the TBRT structure is intrinsically strained.

In order to determine whether the NRs form before or after deposition of the first AlSb barrier, a new sample B was grown. The growth of sample B was terminated after deposition of the InGaAs channel. The InGaAs surface was analyzed by atomic force microscopy (AFM) as shown in Fig. 6. Trenches in two different directions perpendicular to each other can be observed. One of the directions, however, appears to be favored. We believe that these trenches on the InGaAs surface correspond to termination of stacking faults inside the InGaAs layer. By counting the number of trenches (16) along the black dashed line in Fig. 6(b) (1.1 ± 0.2  μm), we obtained an average distance of 69 ± 18 nm, comparable to the one found from STM images (62 ± 14 nm). However, the lateral extent of the ridges seen in the AFM measurements does not correspond to the average base length the NRs observed in the X-STM images. This is due to oxidation of the InGaAs surface imaged by AFM and to the lower resolution of the AFM tip compared with an STM tip.

In our opinion, the trenches function as nucleation points for the formation of NRs. When the first AlSb barrier is grown, Al and Sb fill up the ridges, flattening the surface and resulting in the features we observe in the X-STM images. Indeed, we observed that typically the upper interface of the first AlSb barrier is sharper, despite the presence of NRs.

The AFM measurements gave us also deeper insight into the length and the three-dimensional shape of NRs. In the STM images, we observed a pyramidal or truncated pyramidal cross section shape. However, the STM images do not allow the determination of the actual 3-dimensional shape of the NRs since STM is a surface technique, showing only perpendicular cross sections of the NRs running in one of the two directions. The presence of trenches in the AFM images indicate the NRs have an elongated shape. Hence, the denomination “nanoridges” of the structures seen in the X-STM images.

We analyzed an ULTRARAM sample by X-STM and we observed the presence of growth defects in the upper layers of the sample, i.e., channel, TBRT structure, and FG. We observed stacking faults originating at the lower interface of the InGaAs channel and triangular-shaped AlSb accumulations or nanoridges at the upper InGaAs interface. Almost all the stacking faults correspond to the formation of NR. Therefore, we assumed there is a correlation between the stacking faults and the formation of NRs. From AFM measurement of the InGaAs surface of sample B, we observed the presence of trenches at the surface of this layer causing it to be uneven. We believe that the NRs form when the following AlSb layer is deposited. The deposition of the first AlSb flattens the surface and, as a result, the following TBRT layers have sharper interfaces and more uniform thickness. Despite the presence of growth defects, we do not expect the memory device performances to be significantly effected. Indeed, the formation of the NRs and consequent flattening of the subsequent TBRT layers can be seen as an advantageous self-correcting mechanism in the growth.

The ULTRARAM sample A was characterized by XRD and the corresponding simulation was performed. The In(Ga)As and AlSb layers were assumed to be strained with respect to the GaSb buffer layer, which was considered to be completely relaxed. Similarly, the GaSb buffer layer was taken as reference in the FE simulation of the GaSb/InGaAs/TBRT relaxation profile. Therefore, the In(Ga)As layers are tensile strained while the AlSb barrier are compressively strained. The simulated profile deviate slightly from the experimental one partly due to electronic contribution to the X-STM image.

The sample’s epilayers were deposited on a 2” GaAs n-type wafer by molecular beam epitaxy using a Veeco GENxplor system. Following thermal desorption of the native oxide, a 500-nm GaAs buffer layer was deposited at 560 ° C. The As cell was then closed for 10 s to remove the As background from the chamber and the substrate was cooled to 505 ° C under the Sb flux in preparation for a 500-nm GaSb layer. Through careful control of the substrate temperature, III/V flux ratio, and growth rate, an IMF array is formed at the GaAs/GaSb interface11 that completely relaxes the lattice misfit strain in the GaSb. Next, the substrate was cooled to 440 ° C for deposition of a 50-nm n-type Si-doped InAs backgate and a 8-nm AlSb charge blocking layer. A further 20 nm of GaSb was deposited at 505 ° C before the substrate was cooled to 445 ° C for deposition of a 12-nm In0.8Ga0.2As channel layer. Finally, the substrate was cooled to 440 ° C in preparation for deposition of the triple-barrier resonant tunnelling structure and floating gate, which consisted of 1.8 nm AlSb, 3.0 nm InAs, 1.2 nm AlSb, 2.4 nm InAs, 1.8 nm AlSb, and 10 nm InAs. High-resolution x-ray diffraction measurements were carried out on a Bruker D8 Discover system. The copper K- α x-ray beam was conditioned by a two-bounce Ge crystal and collimating optics. The diffracted signal was collected using an one-bounce Ge crystal and scintillation counter. Fitting of ω 2 θ data was carried out using RADS Mercury software. To reduce the number of free parameters in the fitting model, the InAs layer thicknesses were linked using a fitting parameter, a, such that T n I n A s = a × T n , t a r g e t I n A s, where T n I n A s are individual InAs layer thicknesses calculated by the simulation and T n , t a r g e t I n A s are InAs layer thicknesses that were expected to have been deposited. A similar method was used for AlSb layers using a fitting parameter, b, such that T n A l S b = b × T n , t a r g e t A l S b. It was also assumed that only the 50 nm InAs back gate and GaSb buffer layer contained any relaxation of the crystal lattice. The X-STM experiments have been performed in a commercial Scienta Omicron low-temperature STM (LT-STM) at liquid nitrogen temperature (LNT) and in a Scienta Omicron room-temperature STM. Both systems work at ultrahigh vacuum (UHV) with a pressure of 4 6 × 10 11 mbar. Rectangular shaped samples of 4 × 8 mm 2 cut from the wafer were clamped in an upright position in a custom sample holder. The samples are loaded in the system and baked at 180 ° C to remove impurities from the surface. The samples are then cleaved and moved inside to the STM for the experiment. When the experiment is performed in the LT-STM, the sample is first cooled down at liquid nitrogen temperature and afterward it is cleaved. In the LT-STM, the cleaved surface remains clean for a relatively extended amount of time (weeks) thanks to the low temperature and the UHV environment. Differently, in the RT system, despite the UHV, a new sample must be cleaved after two days due to deposition of contaminants on the cleaved surface. The STM tips were prepared by electrochemical etching of a polycrystalline tungsten wire in 2 M KOH. The tips are then loaded in the system, baked at 230 ° C, and sputtered with Ar to remove the W oxides that form on the surface.

The AFM experiment was performed at room temperature on a commercial Veeco Dimension III AFM using a Pt-coated Si cantilever with a tetrahedral tip (OMCL-AC240TM-B2).

X-STM and AFM images were processed by Gwyddion. On the images, an initial levelling of data by mean subtraction was applied. No further processing was necessary for AFM images. A sharpening filter was applied on the STM images to better highlight different features present, such as the stacking faults. No artifacts are added to the images through this processing method.

This work was supported by European Union’s Horizon 2020 research and innovation programme under the Marie Skłodowska Curie Grant Agreement No. 956548, project QUANTIMONY, and the EPSRC Future Compound Semiconductor Manufacturing Hub Grant No. EP/P006973/1.

The authors wish to acknowledge Michael Verhage and Niels de Vries for AFM measurements and Raja Gajjela for FE simulations.

The authors have no conflicts to disclose.

Aurelia Trevisan: Data curation (equal); Formal analysis (equal); Investigation (equal); Validation (equal); Visualization (equal); Writing – original draft (lead). Peter D. Hodgson: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Writing – review & editing (supporting). Dominic Lane: Conceptualization (equal); Writing – review & editing (equal). Manus Hayne: Conceptualization (equal); Funding acquisition (equal); Project administration (equal); Writing – review & editing (equal). Paul M. Koenraad: Conceptualization (equal); Data curation (equal); Funding acquisition (equal); Methodology (equal); Supervision (lead); Writing – review & editing (lead).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Published open access through an agreement with Eindhoven University of Technology