We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF6 to O2 gas mix of 4%. This results in a low via resistance, even for scaled structures. The BCB dielectric etch rate and dielectric-to-soft mask etch selectivity are quantified. Electrical measurements on lateral and vertical III-V NW transistors, before and after the back-end-of-line process, are presented. No performance degradation is observed, only minor differences that are attributed to contact annealing and threshold voltage shift.
Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
Stefan Andric, Lars Ohlsson Fhager, Fredrik Lindelöw, Olli-Pekka Kilpi, Lars-Erik Wernersson; Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs. J. Vac. Sci. Technol. B 1 November 2019; 37 (6): 061204. https://doi.org/10.1116/1.5121017
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