Admittance parameters analysis can give useful information on border and bulk traps, including the traps located at the inner interface inside high-k gate stacks. The authors present a theoretical model of the high-k dielectric based MIS tunnel diode that comprises the small-signal response of the traps. The traps are charged and discharged not only by charge exchange with the substrate but also by tunnel currents between the traps and the gate electrode. The assumption of tunnel communication between the traps and the gate electrode enables arbitrary traps geometric distribution and makes the model valid not only for surface and border traps but also for the bulk ones, including traps located at the inner interface inside the gate stack. The small-signal equivalent circuit of the considered MIS structure is transformed into series (CSm, RSm) and parallel (CPm, GPm) depictions, which are commonly used in admittance measurements (C-G-V). The comparison between simulation results and measurement data may be used to determine the trap parameters in the investigated device as it is presented in the paper.
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Research Article| May 24 2019
Determination of border/bulk traps parameters based on (C-G-V) admittance measurements
Special Collection: Conference Collection: 20th Workshop on Dielectrics in Microelectronics
Andrzej Mazurak, Jakub Jasin´ski, Bogdan Majkusiak; Determination of border/bulk traps parameters based on (C-G-V) admittance measurements. J. Vac. Sci. Technol. B 1 May 2019; 37 (3): 032904. https://doi.org/10.1116/1.5060674
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