Here, silicon oxide was formed in a U-shaped trench of a power metal-oxide semiconductor field-effect transistor device by various processes. One SiO2 formation process was performed in multiple steps to create a low-defect Si-SiO2 interface, where first a thin initial oxide was grown by thermal oxidation followed by the deposition of a much thicker oxide layer by chemical vapor deposition (CVD). In a second novel approach, silicon nitride CVD was combined with radical oxidation to form silicon oxide in a stepwise sequence. The resulting stack of silicon oxide films was then annealed at temperatures between 1000 and 1100 °C. All processes were executed in an industrial environment using 200 mm-diameter (100)-oriented silicon wafers. The goal was to optimize the trade-off between wafer uniformity and conformality of the trenches. The thickness of the resulting silicon oxide films was determined by ellipsometry of the wafer surface and by scanning electron microscopy of the trench cross sections. The insulation properties such as gate leakage and electrical breakdown were characterized by current–voltage profiling. The electrical breakdown was found to be highest for films treated with rapid thermal processing. The films fabricated via the introduced sequential process exhibited a breakdown behavior comparable to films deposited by the common low-pressure CVD technique, while the leakage current at electric fields higher than 5 MV/cm was significantly lower.
Multi-staged deposition of trench-gate oxides for power MOSFETs
Note: This paper is part of the Conference Collection from the 20th Workshop on Dielectrics in Microelectronics Conference.
Markus Neuber, Olaf Storbeck, Maik Langner, Knut Stahrenberg, Thomas Mikolajick; Multi-staged deposition of trench-gate oxides for power MOSFETs. J. Vac. Sci. Technol. B 1 May 2019; 37 (3): 032202. https://doi.org/10.1116/1.5080527
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