Low DC-bias silicon nitride anisotropic etching

This paper presents an effective approach for silicon nitride plasma dry etching, with low DC-bias (self-bias) and vertical sidewalls. Four factors were studied: capacitively coupled radio frequency power, inductively coupled plasma power, pressure in the etching chamber, and the combination of etching gases. By meticulously controlling these factors, the authors successfully achieved low DC-bias silicon nitride anisotropic etching without argon bombardment, with DC-bias of only 34 V and etching rate of 40 nm/min. Our new etching recipe can avoid short-circuits effectively when patterning sub-50 nm thick silicon nitride layer as a dielectric layer between two metal layers. Moreover, “beaklike” structures, which were formed during the etching process due to increasing etching DC-bias at the beginning of the etching process, were discovered, understood, and prevented.