A novel half-pitch (HP) 15 nm line pattern multiplication process with simple process steps and low cost-of-ownership using a polystyrene-block-poly(methyl methacrylate) lamellar block copolymer was developed to carry out process verification of directed self-assembly lithography on a 300 mm wafer for practical semiconductor device manufacturing. Electrical yield verification of HP 15 nm metal wire circuits fabricated by the HP 15 nm line pattern multiplication process was carried out on a 300 mm wafer. The electrical yield verification revealed the viability of the HP 15 nm line pattern multiplication process from the perspective of the total practical performance including critical dimension control, defect control, local placement error, line width roughness, line edge roughness, and process windows in the pattern transfer process.

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