As the minimum feature size continues to decrease, the line edge roughness (LER) has become a critical issue to be addressed. The LER is caused by a number of stochastically fluctuating effects involved in the fabrication process using electron-beam lithography. Since the LER does not scale with the feature size, it can significantly limit the minimum feature size and the maximum circuit density that can be achieved in a pattern of nanoscale features. Many of the efforts to decrease the LER in the past took an empirical or trial-and-error approach. In this study, a computational approach is taken in developing effective methods to minimize the LER, taking the critical dimension (CD) error due to the proximity effect also into account. Since the LER and the CD error vary with the resist-depth dimension, a 3D model is employed instead of a 2D model used in most of the previous work. The simulation results show that the proposed methods have potential to provide a practical and effective way to minimize the LER.

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