In this work, the authors propose a 4F2 (F is the length of half pitch) memory cell with a vertical PNPN structure (silicon device with 4 layers doped with p-type, n-type, p-type and n-type dopants, respectively) to increase static random access memory (SRAM) integration density compared to the traditional 6T SRAM cell with an area of 90 ∼ 150F2. Thanks to the simple two-terminal configuration, the cross-point structure with proposed cell can be used in memory design, to achieve the highest density in planar complementary metal oxide semiconductor (CMOS) technology and to be implemented potentially in future three-dimensional integration. Experimental results demonstrate that the fabrication of proposed memory cell is compatible with CMOS process, little impact by process variation and reliability issues. Calibrated simulations display that the proposed cell can be programmed at nanosecond level speed with acceptable power consumption in most memory applications.

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