As the CMOS device dimensions shrink to nanometer scale, the time-dependent VTH variability (heteroskedasticity) becomes evident due to the reduced number of stochastically behaving traps in the gate oxide. Consequently, the bias temperature instability (BTI) lifetime of nanometer-sized devices can only be correctly described in the form of time- (or workload-) dependent distributions. This paper discusses a streamlined procedure to obtain BTI lifetime projections for nanometer-scaled devices from the combination of measurements of a small sample set of nanoscaled devices and several large area test devices.
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