Effect of gate capping configurations and silicon-on-insulator thickness with external stresses on partially depleted metal-oxide-semiconductor field-effect transistors

Silicon nitride gate capping by contact etch-stop layer (CESL) was used in this study to induce high and low tensile and compressive stresses on 50-, 70-, and 90-nm-thick silicon-on-insulator (SOI) $n$-/$p$-metal-oxide-semiconductor field-effect transistors. The devices with thicker SOI show a higher interface state, particularly the highly strained devices, although they exhibit higher transconductance. The transconductances of different CESL configurations are sensitive to the $tSOI$ effect, but the transconductances of different $tSOI$ are less sensitive to external compressive stress compared with those of CESL configurations. The CESL-induced compressive devices show higher piezoresistive coefficients than the tensile CESL devices, yielding an external stress of up to about 45.7 MPa for both longitudinal and transverse configurations. This probably results from nonlinear stress-strain relations on the CESL-induced strained channel.