Transparent dual-gate InGaZnO thin film transistors: OR gate operation

Transparent dual-gate (DG) $InGaZnO4$ thin film transistors for OR logic operation were fabricated on a glass substrate. A $100-nm$-thick $SiO2$ layer used as both top and bottom gate dielectrics was deposited by plasma enhance chemical vapor deposition at $200°C$⁠. Compared to bottom gate, top gate thin film transistors (TFTs) exhibited better device performance with higher saturation mobility, drain current on-to-off ratio, lower threshold voltage, and subthreshold gate-voltage swing. This improved performance was mainly attributed to low process-induced damage or low parasitic capacitance between gate and source/drain and low parasitic resistance between channel and source/drain in top-contact TFT configuration (coplanar type). DG-mode TFTs showed saturation mobility of $∼16.9cm2V−1s−1$⁠, drain current on-to-off ratio of $∼1×106$⁠, subthreshold gate-voltage swing of $∼0.33Vdecade−1$⁠, and threshold voltage of $∼1.25V$⁠. The results demonstrate that DG $InGaZnO4$ TFTs are effective in improving the device performance because the channel layer is modulated independently by a top or, bottom gate signal and are well suited for OR gate operation.