In order to make a viable InP MISFET technology, two major problems remain to be solved: (1) instability in the channel current and (2) variations in the channel mobility with processing. These problems are strongly affected by the chemical and physical structure of the semiconductor/insulator interface. This paper presents results of an investigation of the deposited SiO2/InP interface using XPS, UPS, and ELS combined with transport measurements on special Hall geometry MISFET’s. Physical studies of the SiO2/InP interface using XPS show the presence of a 20–40 Å thick native oxide layer primarily composed of InPO4 next to the InP and In2O3 close to the SiO2. UPS and ELS data suggests that the In2O3 forms a trap level slightly above the conduction band. The variation of the channel mobility with surface field and temperature imply that for these devices, the channel mobility is completely dominated by scattering from interface charges and surface roughness, with only a small contribution arising from the bulk optical phonon.
Influence of interfacial structure on the electronic properties of SiO2/InP MISFET’s
K. M. Geib, S. M. Goodnick, D. Y. Lin, R. G. Gann, C. W. Wilmsen, J. F. Wager; Influence of interfacial structure on the electronic properties of SiO2/InP MISFET’s. J. Vac. Sci. Technol. B 1 July 1984; 2 (3): 516–521. https://doi.org/10.1116/1.582810
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