As an attempt to develop a field emitter array with sub‐half‐micron gate openings for low voltage operation, a new fabrication method has been proposed and demonstrated. The key element of the new process is forming the gate insulator by local oxidation of silicon (LOCOS), resulting in the reduction of the gate hole size due to the lateral encroachment of oxide, ultimately compared with the nitride disc size formed by a conventional contact printer. Feasibility of scaling down the gate hole size of a field emitter to sub‐half‐micron has been proved successfully, and the field emitter with a 450 nm diam gate opening has been fabricated and characterized. For a 2500‐tip array with 450 nm diam gate openings, the anode current of 115 μA(∼50 nA/tip) was measured at the gate voltage of 41 V, while the gate current was less than 0.3% of the anode current. Considering the cathode current level required for flat panel display applications and the measured emission characteristics, the fabricated emitter array is expected to operate at a column drive voltage of about 16 V peak‐to‐peak.
New approach to manufacturing field emitter arrays with sub‐half‐micron gate apertures
Chun Gyoo Lee, Ho Young Ahn, Byung Gook Park, Jong Duk Lee; New approach to manufacturing field emitter arrays with sub‐half‐micron gate apertures. J. Vac. Sci. Technol. B 1 May 1996; 14 (3): 1966–1969. https://doi.org/10.1116/1.588965
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