High density plasma etching processes using chlorine gas have been developed for 0.25 μm polysilicon etching. Polysilicon films on SiO2‐covered 200 mm silicon wafers are masked with photoresist patterns, and then etched downstream using a high density helicon source made by Lucas Labs of Sunnyvale, CA. To enhance the anisotropic etching, ion bombardment is provided by radio frequency (rf) biasing of the sample. Polysilicon trenching can be suppressed by performing a two‐step etching process: the first uses a high energy ion bombardment resulting in high etch rate (250 nm/min) and anisotropy and the second a lower ion energy. The second etching step shows a high selectivity (≳80) of Si over SiO2 and therefore ensures the complete removal of the polysilicon during the overetch time. Perfect anisotropic profiles can be obtained without any trenching or other undesirable anomalies. The optimum etch rate nonuniformity is 6.5% (3σ) when operating the source at maximum rf source power (2500 W), 2 mTorr reactor pressure, and adding 30 sccm of helium to a 50 sccm chlorine discharge. Polysilicon and gate oxide etch rates have been measured using a real time in situ HeNe ellipsometer. Etch rates for polysilicon and oxide increase as a function of rf bias power but show no significant pressure or rf source power dependence. After etching, the 200 mm wafers can be transferred (under high vacuum) to an ultra high vacuum analysis chamber equipped with a Fisons ESCALAB 220i x‐ray photoelectron spectrometer.
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January 1996
This content was originally published in
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena
Research Article|
January 01 1996
Polysilicon gate etching in high density plasmas. I. Process optimization using a chlorine‐based chemistry
F. H. Bell;
F. H. Bell
France Telecom, CNET, 38243 Meylan Cedex,
LPCM UMR 110 IMN, 44072 Nantes Cedex 03, France
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O. Joubert;
O. Joubert
France Telecom, CNET, 38243 Meylan Cedex,
LPCM UMR 110 IMN, 44072 Nantes Cedex 03, France
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L. Vallier
L. Vallier
France Telecom, CNET, 38243 Meylan Cedex,
LPCM UMR 110 IMN, 44072 Nantes Cedex 03, France
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J. Vac. Sci. Technol. B 14, 96–101 (1996)
Article history
Received:
July 07 1995
Accepted:
October 13 1995
Citation
F. H. Bell, O. Joubert, L. Vallier; Polysilicon gate etching in high density plasmas. I. Process optimization using a chlorine‐based chemistry. J. Vac. Sci. Technol. B 1 January 1996; 14 (1): 96–101. https://doi.org/10.1116/1.588441
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