Surface passivation approaches for silicon, germanium, and III–V semiconductors

Semiconductors lie at the basis of (opto)electronic devices, including logic and memory devices, solar cells, displays, lasers, photodetectors, light emitting diodes (LEDs), power devices, and quantum devices.¹ These semiconductors include, but are not limited to, silicon, germanium, group III–V semiconductors, group II–VI semiconductors, perovskites, amorphous oxide semiconductors, and 2D semiconductors. The properties of these semiconductors determine their suitability for certain applications and include their bandgap (direct or indirect), bandgap energy, electron and hole mobilities, dopability, thermal conductivity, (chemical) stability, and toxicity. In Fig. 1, an overview of various group IV, III–V, and II–VI semiconductors is given in terms of their electron and hole mobility, along with their bandgap energy, which already demonstrates the wide variety in terms of the semiconductor properties.

For any semiconductor, the presence of defects and impurities in the semiconductor, or at the semiconductor surface, can greatly affect the performance of the devices they are used in.² Such defects are typically detrimental as they can function as recombination active sites, leading to the loss of charge carriers, or they can trap charge carriers, leading to scattering of charge carriers and a related decrease in mobility. In the bulk of the semiconductor, defects and impurities are generally minimized by advances in material synthesis. At the surface of the semiconductor, typically, a large number of structural defects are present. These defects may stem from unsatisfied bonds where the semiconductor lattice terminates. Furthermore, the interface of a semiconductor with another material, such as an insulator or a metal, can also lead to the formation of defects. The reduction of interface and surface defects is called surface passivation, and it is an active field of research. This can be seen in Fig. 2, which presents the total number of publications on surface passivation, as well as the number of publications of surface passivation of some well-known semiconductors.

The defects at the surfaces and interfaces of semiconductors are becoming increasingly important in device performance. One reason is the continued improvement of the semiconductor bulk quality. To illustrate this, it is insightful to look at the evolution silicon solar cells. The relatively low bulk quality silicon used for solar cells (due to cost) is continuously improved by refining the silicon growth processes.³ This has allowed for steadily increasing bulk charge carrier lifetimes due to a decrease in bulk defects.⁴ Power efficiencies of silicon solar cells are now mainly limited by charge carrier recombination at the surfaces and contact areas of the solar cell.⁵ This is further amplified by the continued reduction in wafer thickness for solar cells. A similar route can also be anticipated for semiconductors other than silicon, i.e., continued improvements in material synthesis can reduce the amount of bulk defects and lead to surface defects becoming a dominant factor. Furthermore, many semiconductor devices are continuously “downscaled,” which leads to increased surface-to-volume ratios. This is exacerbated by a switch from planar to structured nanodevices. Since surface defects are becoming relatively more important, it is critical to understand how they can be passivated such that the performance of devices can be improved.

The most frequently used surface passivation approaches involve the deposition of passivation layers, which may be combined with surface treatments, interlayers, and/or postdeposition treatments. In some cases, providing good surface passivation is a requirement of a (passivation) layer, but not its main purpose. These layers are often not referred to as passivation layers. An example is the gate dielectric in a field-effect transistor (FET). This layer should be a dielectric, and a high dielectric constant (high- $κ$⁠) is preferred. However, because a low number of defects at the dielectric/semiconductor interface is required,⁹ it also needs to act as a passivation layer. In other cases, the main purpose of a layer is passivation, but it may also serve secondary purposes. For example, a passivation layer may also act as a protective layer for the underlying semiconductor. It may serve as an optical coating or antireflection layer. In some cases, it can be useful if the passivation layer can also conduct charge, i.e., serve as a “passivating contact.”⁵ 

In this review, the toolbox for semiconductor surface passivation will be discussed, with a focus on the use of passivation layers. Surface passivation of silicon (Si),^4,10,11 germanium (Ge),^12–14 and group III–V semiconductors^15–19 will be discussed. For group III–V semiconductors, gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride (GaN) will be used as general representatives. Figure 3 provides an overview of these semiconductor materials and a few examples of common semiconductor devices. Table I presents the properties of these semiconductors, along with their main application fields. Silicon has been the dominant semiconductor in electronics and photovoltaics. Germanium has high charge carrier mobilities—much higher than silicon—and is highly interesting for high-performance complementary metal-oxide-semiconductor (CMOS) and quantum applications.^20,21 Gallium arsenide and indium phosphide have been of high interest for a variety of applications due to their direct bandgaps and high mobilities.^22–25 Gallium nitride is used for power devices owing to its wide bandgap, high critical electric field, and high electron saturation velocity²⁶ but is also used in (⁠ $μ$⁠)LED applications.²⁷ While there are more semiconductor materials, we focus on these semiconductors, as they are some of the most commonly used, and will provide insights in the current toolbox for semiconductor surface passivation. However, before going into the details of surface passivation approaches for these semiconductors, it is first discussed in more detail how (surface) defects lead to recombination, and how this may be mitigated by surface passivation.

Charge carrier generation and recombination in semiconductors can occur via various pathways. These processes are theoretically quite well-understood and described. In this section, only a short overview of these processes is given. For a rigorous treatment of charge carrier generation and recombination, the reader is referred to any semiconductor textbook, for example, Sze et al.¹  Figure 4 presents a schematic overview of the charge carrier generation and recombination mechanisms, as well as the interface between a semiconductor and a passivation layer. The individual processes are described in detail in this section.

From a qualitative inspection of the equations above, several insights can be gained:

• Recombination processes (⁠ $U$⁠) scale with the number of excess charge carriers. Auger recombination (⁠ $U Auger$⁠) is proportional to the cube of the number of excess charge carriers. This means that Auger recombination becomes an important recombination process in high injection (high concentrations of excess charge carriers) and for highly doped semiconductors.³⁹ 

• SRH recombination (⁠ $U SRH$⁠) for a single level trap is maximized if $E t= E i$⁠,¹ indicating that the recombination is maximized if the energy level of the trap is near the middle of the bandgap of the semiconductor. This extends to SRH recombination at the surface (⁠ $U surf$⁠), where typically traps with energy levels near the midgap contribute most to the surface recombination.⁴³ 

• The effective charge carrier lifetime is limited by the lowest lifetime recombination processes, i.e., by the highest recombination rate.

To combat the detrimental effects of the surface defects, surface passivation can be used, which can be achieved in two main ways:

1. A reduction in the number of defects at the semiconductor surface, i.e., reducing D $i t$⁠. Mainly a reduction in the number of defects with an energy level close to midgap is effective. This type of passivation is called chemical passivation¹¹ and can be achieved by surface treatments of the semiconductor and/or application of a passivation layer.

2. Reduction of the number of (minority) charge carriers reaching the surface, effectively reducing $n$ and/or $p$ in the equations for the recombination processes. This can be achieved in several ways. One is by (heavily) doping the near surface/interface region, which reduces the minority charge carrier concentration in this region, although it can lead to increased Auger recombination. A second way is by applying a passivation layer that provides a fixed charge density (Q $f$⁠), which can induce band bending near the surface of the semiconductor, and, thus, modifies the surface charge carrier concentrations. This second way is typically referred to as field-effect passivation.

For any device, the combination of the semiconductor and passivation layer requires careful consideration of the important properties of the materials and their interface. Figure 5 presents a TEM image of the interface between a semiconductor and a passivation layer, and a schematic representation. At the interface, it is critical that defects are avoided or passivated, i.e., a low interface defect density (D $i t$⁠) should be achieved. There are several “tools” that may be used to control the interface by avoiding or by passivating defects, such as the use of surface treatments, removal or controlled growth of an oxide interlayer, the use of a passivating interlayer, and the use of deposition processes that are not damaging to the substrate. These may also affect the fixed charge density (Q $f$⁠) to some extent.

In many cases, several of these “tools” are used together and have to be tailored to the combination of the passivation layer and the semiconductor, which introduces significant complexity. Combinations of pretreatment(s), passivation layer(s), and postdeposition treatment(s) are sometimes referred to as a passivation scheme. Some passivation schemes may prove to be effective for passivation of a wide variety of semiconductors, while others may only be highly effective on select few semiconductors. When exploring approaches for surface passivation of a novel semiconductor, it can be beneficial to use passivation schemes of well-known semiconductors. However, in some cases, significant tailoring of the passivation schemes, or even completely new approaches, may be required to achieve adequate surface passivation. If a novel passivation layer or layer stack is investigated, it is important to consider also the pretreatments, interlayers, and postdeposition treatments. Some passivation layers may require the use of a pretreatment and/or an interlayer for effective passivation, while other passivation layers might not require them at all.

In order to obtain passivation layers or layer stacks, whose thicknesses are typically on the order of a few to tens of nanometers, atomic scale processing (ASP) methods are used increasingly often. This is a general term, which refers to a collection of methods, which provide atomic scale control of material processing, including, but not limited to, atomic layer deposition (ALD),^44–47 atomic layer etching (ALE),^48,49 and chemical vapor deposition (CVD).⁵⁰ While a rigorous treatment of these methods is beyond the scope of this work, an overview of ASP methods and various important aspects of these methods is shown in Fig. 6. The importance of the various aspects, such as throughput or uniformity, often depends on the intended application, and every method has its own strengths. For deposition of passivation layers, CVD and ALD are frequently used, and these processes have enabled the deposition of a wide variety of (passivating) thin-films. It is noted that the switch to 3D structured devices will lead to 3D compatible deposition methods, such as ALD, to become increasingly important. In Secs. III–V, the approaches for passivation of silicon, germanium, and III–V semiconductors are discussed.

The first transistor—invented at Bell Labs in 1947—did not feature silicon, but a germanium crystal as the semiconductor.⁵¹ At that time, research of semiconductors focused on both silicon and germanium. Germanium could already be made with high purity by a process called zone-refining, while this process was only later developed for silicon.^51,52 Ultimately, the discovery of the high-quality interface between silicon and silicon oxide led to silicon becoming the dominant semiconductor. The silicon/silicon oxide (Si/SiO $x$⁠) interface is arguably the most well-characterized semiconductor/oxide interface, and it has played a critical role in the development of electronic and photovoltaic devices.

A layer of SiO $x$ on Si may form unintentionally due to contact of the Si surface with ambient oxygen or water,⁵³ but it also may be formed intentionally by surface oxidation or the deposition of an oxide (passivation) layer. Since SiO $x$ can form a stable and high-quality interface with silicon, it is often used for passivation in silicon-based devices, resulting in low values of the interface defect density (D $i t$⁠).

Several defects occurring at the Si/SiO $x$ interface have been identified by electron spin resonance (ESR), including P $a$⁠, P $b$⁠, and P $c$-type defects.⁵⁴ The P $b$-type defects are identified as the most important defects at this interface,⁵⁵ and consist of three variants depending on the Si orientation, namely, the P $b$-defect at the (111)Si/SiO₂, and the P $b 0$ and P $b 1$-defects at the (100)Si/SiO₂ interface.⁵⁶ Various studies have reported the correspondence between the P $b$-type defects and D $i t$⁠,^57–62 suggesting that the P $b$-type defects are mainly responsible for D $i t$ at the Si/SiO $x$ interface. This correspondence can also be seen in the inset of Fig. 7. The P $b$ and P $b 0$-defects have the structure • $Si ≡ S i 3$⁠, i.e., an unsatisfied silicon atom bonded to three silicon atoms and are often referred to as a dangling bond. The P $b 1$-defect also has an unpaired Si bond but is assigned to a distorted interfacial dimer.⁶³ Since the P $b$-type defects are mainly responsible for the interface defect density at the Si/SiO $x$ interface, it is important that they are passivated.

The passivation reaction [Eq. (8)] occurring at the (100)Si/SiO $x$ interface is schematically represented in Fig. 8. The incoming H₂ can react with the P $b$-type defects, leading to passivation of the silicon dangling bond. It is noted that SiO₂ layers formed by silicon oxidation are typically considered to be amorphous but can in some cases be (partly) epitaxial.⁶⁷ The passivation reaction [Eq. (8)] typically has lower activation energies than the depassivation reaction [Eq. (9)].⁶⁶ In addition to molecular hydrogen (H₂), atomic hydrogen (H) can also lead to passivation of the P $b$-type defects.⁶⁵ The hydrogen required to passivate the dangling bonds can come from various sources, for example, from a hydrogen-rich annealing ambient, but also from hydrogen-rich passivation layers, or from hydrogen plasma treatments. A (postdeposition) annealing treatment is typically required to deliver the hydrogen to the Si/SiO $x$ interface and to activate the (chemical) passivation by hydrogen [Eq. (8)].

Annealing is a heat treatment, and typical temperatures range from 250 to 500  $°$C. Annealing may be conducted in various ambients, such as nitrogen, argon, or forming gas. Annealing at too high temperatures or for too long often leads to depassivation due to the breaking of Si–H bonds [Eq. (9)] and effusion of hydrogen, as also illustrated by the increase in D $i t$ from the red dash curve to the blue dash dot curve in Fig. 7. For many passivation schemes on silicon, this leads to a U-shaped curve for S $eff$ as a function of annealing temperature, which is shown in Fig. 9. Annealing first activates the passivation, where the hydrogen originates from the passivation layer or another source, which leads to a decrease in S $eff$⁠. However, when the annealing temperature becomes too high, S $eff$ increases due to breaking of Si–H bonds and effusion of hydrogen. The optimum in passivation quality (lowest S $eff$⁠) is likely determined by the balance between the passivation [Eq. (8)] and depassivation [Eq. (9)] reactions,⁶⁸ and the amount of hydrogen available at the silicon surface. In some cases, annealing also activates the field-effect passivation of a passivation scheme by leading to an increase in the fixed charge density (Q $f$⁠). This has, for example, been observed to be the case for aluminum oxide (Al₂O₃) deposited on silicon by thermal ALD.⁶⁹ 

One very particular postdeposition annealing treatment for SiO $x$ is the so-called alneal, where an aluminum metal layer is deposited on the SiO $x$⁠, followed by an annealing step. This has led to extremely low S $eff$ values,⁷⁰ which is assumed to be related to passivation of silicon dangling bonds by atomic hydrogen, which may be formed due to reactions between the aluminum, and water or hydroxyl ions present in or on the SiO $x$⁠.⁷¹ 

Stoichiometric silicon oxide (SiO₂) is an insulator with a wide bandgap of around 9 eV and a dielectric constant of 3.9.⁷⁹ However, the stoichiometry of a layer often depends on the preparation method, and the native silicon oxides present on a silicon surface are not necessarily stoichiometric. The same holds for the quality of the interface between Si and a (native) SiO $x$ layer, which can vary significantly. Typical D $i t$ values for the Si/SiO $x$ interface are 10¹² cm ^$−$2 eV ^$−$180 but can range from 10¹⁰ to 10¹³ cm ^$−$2 eV ^$−$1 depending on how the SiO $x$ is obtained. In addition to possibly leading to very low D $i t$ values, SiO $x$ also provides a low positive fixed charge density (Q $f$⁠) on silicon, which is on the order of +10¹¹ cm ^$−$2.¹⁰ 

When SiO $x$ is used for passivation, the (low-quality) native oxide is often removed by wet-chemical etching and then a (high-quality) SiO $x$ layer is formed in a controlled way. In this way, a high-quality Si/SiO $x$ interface with low D $i t$⁠, i.e., a well-passivated silicon surface, is straightforward to obtain. Removal of SiO $x$ is typically achieved by etching using hydrofluoric acid (HF),⁸¹ while SiO $x$ can be formed on silicon by thermal oxidation,⁸² plasma oxidation,⁸³ UV/O₃ oxidation,⁸⁴ or wet-chemical oxidation.⁸⁵ Some well-known wet-chemical oxidation methods are Radio Corporation of America (RCA) clean, H₂SO₄:H₂O₂, and HNO₃.^84–86 

The SiO $x$ can act as a passivation layer by itself, but often, it serves as an interlayer for other passivation layers. Many of the passivation layers shown in Fig. 9 also have an SiO $x$ interlayer. The (SiO $x$⁠) interlayer provides a good interface, while the passivation layers can provide hydrogen for further passivation of the dangling bonds at the interface or can provide other benefits in a device. It is noted that an SiO $x$ interlayer does not have to be stoichiometric to provide a good interface. This has been observed for niobium oxide (Nb₂O₅) on silicon, which provides good passivation with a substoichiometric silicon oxide interlayer.⁸⁷ The use of oxide passivation layers (such as Al₂O₃⁸⁸) on silicon often inevitably leads to the formation of an SiO $x$ interlayer, either during the deposition of the oxide or during a subsequent annealing treatment.

Therefore, the (chemical) passivation mechanism of many oxide passivation layers on silicon is typically also attributed to the passivation of silicon dangling bonds at the Si/SiO $x$ interface by hydrogen. This is qualitatively shown in Fig. 10, which shows the electrically detected magnetic resonance (EDMR) spectra of as-deposited and annealed Al₂O₃ on silicon. Several defects, including a P $b$-type defect (g = 2.0087 and g = 2.0036), could be identified in the as-deposited state.⁶⁹ After annealing, the EDMR spectra no longer reveals the presence of the defect states, which is in agreement with the low D $i t$ (⁠ $≤$ 10¹¹ cm ^$−$2 eV ^$−$1) obtained after annealing. Additionally, it is reported that Si/Al₂O₃ and Si/HfO₂ interfaces (without SiO $x$ interlayers) also exhibit P $b$-type defects.^89,90 The chemical passivation mechanism of many passivation layers on silicon is, thus, thought to be similar and related to hydrogen passivation of silicon dangling bonds.

Several passivation schemes that have been investigated on silicon were already shown in Fig. 9. Clearly, not all passivation schemes result in the same passivation quality. Optimization of surface pretreatments, deposition conditions, and postdeposition annealing conditions or other postdeposition treatments can lead to improvements in passivation quality. This optimization has been the subject of significant research over the past few decades and has already provided an extensive toolbox for passivation of silicon. This can be visualized by the overview of D $i t$ and Q $f$ values for various passivation schemes on silicon, as shown in Figs. 11(a) and 11(b), respectively. Wide ranges of D $i t$ and Q $f$ values have been reported, even for the same passivation scheme, which can be attributed to widely varying processing conditions. In principle, a low D $i t$ is desired, but sometimes even higher D $i t$ values may be acceptable if the passivation scheme provides other benefits, such as improved stability. The stability of the passivated interface is highly important since the passivation quality can degrade over time due to device operation or harsh external environments (e.g., high intensity radiation or high temperatures).

Figures 9 and 11 illustrate the wide variety of passivation schemes that have been investigated for silicon. Several additional passivation layers that have been investigated on silicon include TiO $x$⁠,⁹¹ MoO $x$⁠,⁷⁵ Ta₂O₅,⁹² ZrO₂,⁹³ and AlN,⁹⁴ which each have their own benefits.⁷⁵ Furthermore, not only the use of different materials, but also the use of stacks of passivation layers can provide benefits. For example, using an Al₂O₃ capping layer on ZnO leads to improved stability, as well as an increase in the charge carrier density and mobility of the ZnO layer after annealing, as compared to a single layer of ZnO.⁹⁵ The increase in mobility is thought to be related to hydrogen passivating defects and traps at grain boundaries of the ZnO.⁹⁵ Capping of ZnO by Al₂O₃ furthermore led to improved passivation quality of the ZnO.⁹⁶ Another example is the use of SiN $x$ for capping Al₂O₃, which improves the high temperature stability of the Al₂O₃ layers.⁹⁷ These examples illustrate that the use of stacks of materials can be a powerful tool to tailor passivation schemes to an application. In the remainder of this section, some of the most used and most interesting passivation schemes for silicon surface passivation will be discussed in more detail. The typical properties of these passivation schemes are presented in Table II.

In addition to SiO $x$⁠, other Si-based layers, such as hydrogenated amorphous silicon (a-Si:H), polysilicon (poly-Si), silicon carbide (SiC), and silicon nitride (SiN $x$⁠), may be used for passivation of silicon, either as a passivation layer or an interlayer.

The a-Si:H layers typically provide excellent chemical passivation of silicon, because they terminate the Si dangling bonds by continuing the c-Si lattice into a disordered network of Si–H and Si–Si bonds.¹¹² Therefore, they are also great interlayers for passivation and are frequently used in conjunction with other layers. In addition to functioning as a passivation layer, a-Si:H has also been used as channel materials for thin-film transistors (TFTs); however, amorphous oxide semiconductors and 2D semiconductors are now also being used as channel materials.¹¹³ It is noted that TFTs devices can also benefit from passivation.

Semi-insulating poly-Si was used early on as a passivation layer for bipolar Si transistors, as it could protect the device against contamination and externally applied electric fields.¹¹⁴ Later, structures combining doped poly-Si with a thin SiO₂ interlayer (tunnel oxide) were realized as “passivating contacts” for applications in solar cells.^5,115 The solar cell concepts referred to as silicon heterojunction (SHJ) and tunnel oxide passivated contact (TOPCon) feature a-Si:H and poly-Si passivating contacts, respectively. Both concepts have enabled very high power efficiencies above 26%.¹¹⁶ The Si/SiO₂ interface of the poly-Si typically requires hydrogenation (i.e., passivation of silicon dangling bonds using hydrogen), which is often accomplished by using a H₂ plasma treatment, or by deposition of hydrogen-rich layers, such as Al₂O₃, SiN $x$⁠, or Al₂O₃/SiN $x$ stacks on top of the SiO₂/poly-Si stack followed by an annealing treatment.^{77,115,117–119}

SiC can be used for passivation of silicon, and it has been shown that SiO $x$/SiC stacks can also act as passivating contacts on silicon, where the SiO $x$ again acts as a tunnel oxide.¹²⁰ An advantage of the SiO $x$/SiC stacks is that they are highly transparent. In power electronics, SiC is used as a semiconductor, mainly in high power and high temperature devices. In those cases, the SiC requires passivation, where SiO $x$ is typically used. However, it is challenging to obtain a high-quality SiC/SiO $x$ interface, mainly due to the presence of carbon-related defects.^121,122 Note the difference between the Si/SiO $x$/SiC and the SiC/SiO $x$ interfaces. In the former case, Si is the semiconductor that is passivated. In the latter case, SiC is the semiconductor that is passivated.

SiN $x$ is frequently used as a passivation layer for silicon, but it can also serve as a capping layer for other passivation layers. It is furthermore often used as a combined passivation layer and antireflection coating for solar cells.^100,123 SiN $x$ can achieve quite good chemical passivation of silicon with D $i t$ values down to 10¹¹ cm ^$−$2 eV ^$−$1. Depending on the nitrogen content in SiN $x$⁠, its properties can be vastly different.¹⁰⁰ For example, the bandgap can vary from 2.9 to 5.3 eV depending on the N/Si ratio.¹⁰¹ The passivation of silicon is also affected by the composition of SiN $x$⁠, “Si-rich” SiN $x$ is reported to have better as-deposited passivation quality, while “N-rich” SiN $x$ is more thermally stable.¹²⁴ SiN $x$ is characterized by a high positive fixed charge on the order of +10¹¹–10¹³ cm ^$−$2 on silicon. The magnitude of the fixed charge also appears to be impacted by the composition, with “Si-rich” SiN $x$ typically having lower Q $f$⁠.¹²⁵ The origin of the positive fixed charge in SiN $x$ is attributed to K-centers (⁠ $∙ Si ≡ N 3$⁠) and N-centers (⁠ $∙ N = S i 2$⁠), both of which can also act as dangling bonds and contribute to D $i t$⁠.¹²⁶ This means that an increase in Q $f$ in SiN $x$ is typically paired with an increase in D $i t$⁠. Therefore, SiN $x$ typically has either low D $i t$ or high Q $f$⁠, but not both at the same time. It is noted that these N- and K-centers are amphoteric, yet SiN $x$ on silicon is almost exclusively positively charged.

Al₂O₃ is a dielectric with a bandgap of 6–9 eV and a dielectric constant of 7–9.^18,69 It is currently one of the most frequently used passivation layers, not just for silicon surface passivation, but also for germanium and III–V semiconductors, as will be shown later. On silicon, Al₂O₃ is used in a myriad of electronics and photovoltaics applications. Furthermore, Al₂O₃ is frequently used as a capping layer for other passivation layers, likely because it can provide chemical stability, and may act as a hydrogen source/effusion barrier.

For silicon solar cells, Al₂O₃ was already reported in 1989 by Hezel and Jaeger,¹²⁷ but it remained largely unnoticed until 2008.¹²⁸ It has since enabled the transition from the aluminum back surface field (Al-BSF) solar cell design to the passivated emitter and rear cell (PERC) design,¹²⁹ which enables solar cell power efficiencies up to 24%. It is also featured on the front side of the TOPCon solar cell, the successor of the PERC solar cell.

Al₂O₃ provides excellent chemical passivation of silicon, with an interface defect density as low as 10¹⁰ eV ^$−$2 cm ^$−$1. It is furthermore characterized by a rather high negative fixed charge density (Q $f$⁠) of around $−$10¹² cm ^$−$2. Due to this high Q $f$⁠, Al₂O₃ is not very well-suited for CMOS, as this leads to threshold voltage shifts. The origin of the fixed charge in Al₂O₃ is not yet fully understood.¹³² It has been attributed to negatively charged AlO₄ tetrahedrals, which may occur preferentially at the Al₂O₃/SiO $x$ interface, as the silicon oxide is also tetrahedrally coordinated.¹³³ Furthermore, interstitial oxygen and aluminum vacancies were also shown to be preferentially negatively charged and could contribute to the negative Q $f$⁠.^132,134

HfO₂ is another high- $κ$ dielectric that has been investigated extensively for CMOS technology.¹³⁵ The dielectric constant of HfO₂ can vary significantly depending on phase, but typically ranges between 10 and 25.¹⁰⁴ Quite low surface recombination velocities can be achieved by using HfO₂¹⁰⁶ due to relatively low D $i t$ values of 10¹¹ cm ^$−$2 eV ^$−$1. Since the magnitude of Q $f$ is relatively low, it is well-suited for CMOS applications. Interestingly, both negative and positive values for Q $f$ have been reported for HfO₂ on silicon.^74,105,106 Annealing could result in a switch from positive to negative Q $f$⁠.¹⁰⁵ In addition to acting as a high- $κ$ gate dielectric and a passivation layer, ferroelectric HfO₂-based materials have also attracted significant attention for nonvolatile memory applications.¹³⁶ 

PO $x$/Al₂O₃ stacks have shown a unique combination of a very low defect density (⁠ $∼$10¹⁰ cm ^$−$2 eV ^$−$1) and a simultaneous very high positive fixed charge density (+10¹²–10¹³ cm ^$−$2) on silicon. Therefore, these stacks have been investigated extensively over the past few years.^76,107–111 The stack has a bandgap of >6 eV and a dielectric constant of 6.4–7.4.^76,107 The Al₂O₃ layer serves as a capping layer, because the PO $x$ is highly hygroscopic. However, the Al₂O₃ layer also plays a role in the chemical passivation mechanism of the PO $x$/Al₂O₃ stack. This mechanism is thought to be related to passivation of silicon dangling bonds by hydrogen, where the hydrogen is mobilized by the formation of AlPO₄ upon annealing.¹⁰⁷ The combination of a very low D $i t$ and a high positive Q $f$ has shown to lead to state-of-the-art passivation of n-type doped silicon, with a passivation quality on par with SiO $x$/SiN $x$/SiO $x$ stacks and alnealed SiO $x$⁠.¹⁰⁸ Although the origin of this high positive fixed charge remains unknown, it has been suggested that positively charged PO₄ tetrahedrals in the PO $x$⁠, analogous to the negatively charged AlO₄ tetrahedrals in Al₂O₃, may be the entities responsible for the positive fixed charge in the PO $x$/Al₂O₃ stacks.¹⁰⁹ 

In contrast to the silicon/silicon oxide interface, the germanium/germanium oxide (Ge/GeO $x$⁠) interface does not easily result in a high-quality interface. The native oxide of germanium is typically viewed as a poor oxide, as it is thermally unstable and water soluble.^12,14,137 This has hampered the development and scaling of germanium devices. Nevertheless, the high carrier mobilities of germanium, combined with its compatibility with silicon, have made it to be a highly interesting semiconductor for a wide variety of applications, including transistors, quantum technology, and (infrared) photonics. Furthermore, hexagonal germanium and silicon-germanium alloys exhibit a direct bandgap¹³⁸ and can be used in applications that require efficient light emission, such as LEDs and lasers.

The defects occurring at the Ge/GeO $x$ interface have been investigated by ESR, similarly as for the Si/SiO $x$ interface. However, ESR has been unable to detect Ge dangling bonds at the Ge/GeO $x$ interface.^139,140 It is suggested that the energy level of the Ge dangling bond is located below the germanium valence band maximum.^141,142 This would mean that the Ge dangling bond is only stable in a negative charge state, and therefore not observable by ESR.¹⁴⁰ It has furthermore been suggested that interstitial hydrogen in germanium acts only as an acceptor,^139,142,143 which would mean that the Ge dangling bond and the hydrogen would repel each other, making hydrogen passivation unlikely.

Although ESR has been unsuccessful at measuring the Ge dangling bond defect, it has been reported on the basis of density functional theory (DFT) that a Ge dangling bond defect at the Ge/GeO₂ interface may have an energy level near the middle of the Ge bandgap.¹⁴⁴ This dangling bond has the structure of $∙ Ge ≡ G e 3$⁠, similar to the Si dangling bond. However, this Ge dangling bond density may be below the ESR detection limit, and therefore not observed.¹⁴⁴ This Ge dangling bond may be passivated by hydrogen, but it is unknown whether it is really present at the Ge/GeO $x$ interface.

On silicon-germanium alloys (SiGe), an interfacial Ge dangling bond was identified by ESR.¹⁴⁵ This defect, denoted GeP $b 1$ present at the SiGe/SiO $x$ interface, can be passivated with hydrogen, following reactions similar to Eqs. (8) and (9). However, the same dangling bond is not observed for Si $1 − x$Ge $x$ alloys with compositions x < 0.45 and x > 0.87,¹⁴⁵ i.e., for “Si-rich” and “Ge-rich” compositions.

From the discussion above, it appears that there is no consensus yet on the defects occurring at the germanium interface, and the role of hydrogen for passivation of germanium surfaces is not fully understood yet. Nevertheless, hydrogen does appear to play a role for the passivation of defects at the germanium surface. This is, for example, apparent in devices and passivation studies of germanium, where it is reported that postdeposition treatments involving hydrogen can result in positive effects, such as a reduction of D $i t$^146,147 and a decrease in S $eff$⁠.^148–151 This is illustrated in Fig. 12, which reveals some similarities and differences for passivation of silicon and germanium by Al₂O₃ and PO $x$/Al₂O₃. The U-shaped curves are also observed for germanium, which suggests the passivation of defects on germanium by hydrogen. However, it is not as straightforward to obtain low S $eff$ on germanium with Al₂O₃, as indicated by the high S $eff$ in comparison with silicon. It is noted that excellent passivation of germanium by Al₂O₃ is possible, but it requires the use of interlayers or surface treatments to control the interface, as will be shown later. For PO $x$/Al₂O₃ on germanium, a much lower optimal annealing temperature is observed as compared to PO $x$/Al₂O₃ on silicon.

These similarities and differences between passivation of silicon and germanium are also reflected in the passivation approaches of germanium. On germanium, the passivation approaches tend to focus on obtaining high-quality interfaces, rather than passivating the remaining defects on the interface with hydrogen. Even though the focus may be slightly different, many approaches and materials used are still similar to passivation of silicon.

The native oxide of germanium is typically removed prior to any further processing, similar as for silicon. Wet-chemical removal of the native GeO₂ may be done using HF, HCl, and HBr.¹⁵² HF removes the GeO₂, but the suboxides remain, while HBr removes all germanium oxides.¹⁵² It has been shown that intentionally grown GeO₂ can serve as a good passivating (inter)layer on germanium. Stoichiometric germanium oxide (GeO₂) has a bandgap of 4.7 eV¹⁵³ and a dielectric constant of around 5.5–5.9.¹⁵⁴ Thermal oxidation resulted in Ge/GeO₂ interfaces with D $i t$ values down to 10¹¹ cm ^$−$2 eV ^$−$1.¹⁵⁴ Even higher quality Ge/GeO₂ interfaces were reported for GeO₂ obtained by electron-cyclotron-resonance oxygen plasma treatments, resulting in D $i t$ values down to 6 $×$ 10¹⁰ cm ^$−$2 eV ^$−$1.¹⁵⁵ These high-quality GeO₂ layers can serve as an interlayer for passivation schemes, an approach similar to passivation of silicon. It was, for example, found that the good passivation quality of GeO₂ is retained when combined with high- $κ$ dielectrics, such as Al₂O₃ and HfO₂.^156–158 

The high charge carrier mobilities of germanium have made it a promising candidate to use as a channel material in FETs, and therefore, the use of high- $κ$ dielectrics on germanium has been investigated quite extensively.¹⁷⁵ This can be seen in Fig. 13, which provides an overview of reported interface defect densities (D $i t$⁠) of several passivation schemes on germanium. Many of these passivation schemes combine interlayers or surface treatments with high- $κ$ dielectrics. Typical D $i t$ values of high- $κ$ dielectrics on germanium are around 10¹¹–10¹² cm ^$−$2 eV ^$−$1. The investigations in controlling and obtaining high-quality germanium interfaces with high- $κ$ dielectrics for FET devices are now also enabling the use of germanium in quantum technologies.²¹ 

Thin epitaxial silicon layers have been used for germanium surface passivation, mainly as an interlayer for high- $κ$ dielectrics in transistor applications.^{158,166–168} This strained Si interlayer may not be too thick, as otherwise, it may relax, which can lead to the formation of defects. It also cannot be too thin, as otherwise, it may be fully oxidized by subsequent oxide (gate dielectric) deposition.¹⁵⁸ The optimal Si layer thickness is between four and eight monolayers. If the defects at the Ge/Si interface are not limiting, the passivation of these epitaxial Si layers reduces back to passivation of silicon surfaces. It is shown that very low interface defect density values on the order of 10¹⁰ cm ^$−$2 eV ^$−$1 can be achieved,¹⁶⁶ but also, significantly higher values for D $i t$ on the order of 10¹² cm ^$−$2 eV ^$−$1 have been reported.^167,168

Passivation of germanium by SiN $x$ has recently been investigated and may be used in infrared photodetectors and multijunction solar cells.^150,176 As discussed previously, SiN $x$ leads to relatively low defect densities on silicon, along with a moderate positive fixed charge. On germanium, the defect density of the Ge/SiN $x$ interface is determined to be around 4  $×$ 10¹¹ cm ^$−$2 eV ^$−$1.¹⁵⁰ However, interestingly, SiN $x$ on germanium results in a negative fixed charge.^150,176 The use of a SiN $x$/Al₂O₃ stack and subsequent annealing treatments further improved the effective charge carrier lifetimes, suggesting hydrogen passivation of the Ge interface defects, although it did appear to be less efficient than hydrogenation of the Si interface by the same stack.¹⁵⁰ 

Similar as to silicon, a-Si:H thin-films can be used as a passivation layer and as an interlayer for germanium. They have, for example, been used as passivation layers for Si/SiGe quantum wells.¹⁷⁷ Furthermore, stacks of a-Si:H with Al₂O₃ were highly effective for passivation of germanium, as discussed in Sec. IV F.¹⁴⁹ 

Passivation of germanium by Al₂O₃ is investigated not only for its role as a high- $κ$ dielectric in transistors,^153,157,171 but may also be used in radiation detectors, and hexagonal Ge-based LEDs and lasers.^{148,149,178,179} Isometsä et al. reported that using a HF pretreatment and subsequent deposition of Al₂O₃ by ALD followed by annealing in N₂ resulted in an S $eff$ of 14.9 cm/s.¹⁷⁸ Using a HCl pretreatment instead led to an S $eff$ of 6.6 cm/s. This improvement was shown to be mainly due to an increase in the negative Q $f$ of Al₂O₃. Berghuis et al. reported a significantly higher S $eff$ of 1000 cm/s for ALD Al₂O₃ on germanium, which was also pretreated by HF.¹⁴⁸ Later, a very low S $eff$ value of 2.7 cm/s was obtained by using HF pretreatment and an a-Si:H interlayer prior to deposition of Al₂O₃.¹⁴⁹ 

The use of an a-Si:H interlayer mainly resulted in a higher Q $f$⁠, which is suggested to be related to the formation of a SiO $x$ interlayer between the a-Si:H and Al₂O₃ layers.¹⁴⁹ Using thermal ALD instead of plasma-enhanced ALD for deposition of the Al₂O₃ layer resulted in a lower Q $f$⁠, which may be related to the thinner SiO $x$ layer that forms between the a-Si:H and Al₂O₃.¹⁴⁹ This can be seen in Fig. 14, where the SiO $x$ layer in Fig. 14(a) is thicker than in Fig. 14(b).

These examples of germanium passivation by Al₂O₃ underline that pretreatments and interface control are highly important in obtaining excellent passivation quality of germanium. In these cases, the improvement of passivation quality was mainly attributed to an increase in the negative fixed charge, rather than a decrease in the interface defect density. It is noted that many passivation schemes—such as Al₂O₃ and SiN $x$—provide a negative fixed charge on germanium. In contrast, the PO $x$/Al₂O₃ stacks were found to provide a positive fixed charge on germanium.¹⁵¹ Additionally, the deposition of PO $x$/Al₂O₃ stacks appears to lead to removal and reduction of the GeO $x$⁠.¹⁵¹ This may explain why low S $eff$ values were more straightforward to obtain with PO $x$/Al₂O₃ on germanium as compared to Al₂O₃ on germanium (Fig. 12) since for Al₂O₃ on germanium, a GeO $x$ interlayer was present.¹⁴⁸ 

Another approach for surface passivation is to use nitridation of the surface (analogous to the use of SiN $x$ on silicon), resulting in a GeO $x$N $y$ or GeN $x$ surface layer.^159–162 The general idea is that GeN $x$ is thermally stable and insoluble in water, unlike the GeO $x$⁠. Nitridation of the surface can be achieved by thermal or plasma processes using NH₃ or N₂ gas. The GeO $x$N $y$ layers can serve as an interlayer for other passivation layers or can serve as a dielectric passivation layer by itself. The range of D $i t$ values for various GeO $x$N $y$/Ge interfaces is given in Fig. 13. Note that different capping layers were used on top of the GeO $x$N $y$⁠, such as Ta₂O₅,¹⁵⁹ HfO₂,¹⁶⁰ and SiN $x$⁠,¹⁶¹ which may also affect the resulting D $i t$ values. It is reported that surface nitridation leads to a positive Q $f$⁠, indicated by a negative flatband voltage shift.¹⁶³ Annealing was reported to lead to a reduction of the fixed charge.¹⁶³ 

Passivation of germanium surfaces by sulfur has been investigated quite intensively.¹⁴ Sulfur passivation may be achieved by using an (NH₄)₂S solution^180–182 or H₂S gas.^183,184 Desorption of S from the germanium surfaces without a capping layer occurs at temperatures above 320  $°$C in an ultrahigh vacuum (UHV). It was, however, found that S-passivated germanium with an HfO₂ capping layer results in a D $i t$ of 2.4 $×$ 10¹² cm ^$−$2 eV ^$−$1, which was lower than the D $i t$ of 5.9 $×$ 10¹² cm ^$−$2 eV ^$−$1 for a nitridated germanium reference.¹⁸⁰ Furthermore, the S-passivated germanium resulted in a less flatband voltage shift compared to the nitridated reference, indicating the presence of a less fixed charge at the interface. For germanium capacitors with a HfON gate dielectric, it was found that the EOT and D $i t$ were both lower for S-passivated samples as compared to those without S-passivation.¹⁸¹ It is noted that sulfur passivation also works on silicon¹⁸⁵ but is generally not frequently used.

Surfaces of III–V semiconductors have been quite challenging to passivate, which has significantly hampered the development of III–V based devices.^15–18 One of the challenges is the native oxides forming interfaces with a high number of defects, which can lead to Fermi-level pinning.¹⁸⁶ Spicer et al.¹⁸⁷ suggested that these defects form indirectly as a result of adatoms on the surface, which was based on the observation that the Fermi-level pinning was similar for metals and oxygen adatoms. In this section, first GaAs and InP will be treated as general representatives of III–V semiconductors, and then GaN will be discussed to illustrate the effect of passivation layers in devices.

At the interfaces of GaAs and InP, several structural defects—which may result in Fermi-level pinning—have been suggested to occur. At GaAs interfaces, the presence of As $G a$⁺ antisites (an arsenic atom replacing a gallium atom in the lattice), Ga and As dangling bonds, As-As dimers, and several defect complexes has been suggested.^15,16,18,188 The As-As dimers and the As $G a$⁺ antisite are thought to be some of the main defects occurring at the GaAs interface.^16,189 At the InP interfaces, the presence of phosphorus and indium vacancies (V $P$ and V $I n$⁠), interstitials, antisites (P $I n$ and In $P$⁠), and dangling bonds has been suggested.^190,191 In a phosphorus-rich material, V $I n$ and P $I n$ antisites appear to dominate, while in an indium-rich material, the dominant defect appears to be the V $P$⁠.¹⁹² 

Although some of the defects occurring at the III–V surfaces and interfaces may be passivated by hydrogen,^15,193–195 the main approaches for passivation of III–V semiconductors focus on management of the interface and avoiding the formation of the defects in the first place, similar to passivation of germanium. Clearly, avoiding the formation of defects is always preferred, even on silicon, but it is much more critical for semiconductor interface defects that are not easily passivated by hydrogen. This also illustrates why silicon is more straightforward to passivate as compared to germanium and III–V semiconductors. On silicon, a good interface can be obtained with SiO₂ (or a-Si:H) as an interlayer, which can be used together with a wide variety of passivation layers. The defects at those interfaces can often be further passivated by hydrogen. On germanium and III–V semiconductors, the passivation layer itself needs to provide a good interface, and the possibility to repair defects at the interface by hydrogen is limited. Furthermore, oxidation of the semiconductor during processing should typically be avoided, as this may lead to additional defects at the interface. This puts significantly higher requirements on the passivation schemes and processing methods for germanium and III–V semiconductors as compared to silicon and, therefore, makes interface management significantly more important.

The various surface passivation approaches used for III–V semiconductors include the deposition of (high- $κ$⁠) dielectrics, Si-based interlayers, S-based surface treatments, plasma treatments, and nitridation.^16–19,53 Furthermore, wet-chemical etching steps of the native oxides, such as those involving HF, HCl, or NH₄OH, are often used prior to other passivation approaches.¹⁹⁶ The S-based surface treatments also effectively remove the native oxides and lead to passivation by forming S-based covalent bonds at the surface for many III–V semiconductors.¹⁹⁷ These approaches bear significant similarities to those used for silicon and germanium.

This reaction is thought to be favorable in weak oxidation conditions, and the elemental As may act as a defect at the native oxide surface.

For InP, it has been shown for many different methods of oxidation of InP surfaces that the oxides are a mixed InP $x$O $y$ state, which is thought to be present as a nonstoichiometric amorphous phase.²²⁰ Interestingly, for InP, it is shown that devices with a low interface defect density can be obtained by utilizing the native oxide.^221,222 Specifically, phosphorus-rich oxides, such as In(PO₃)₃, grown by chemical or electrochemical treatments, were used.²²² Such phosphorus-rich oxides can also reduce the out-diffusion of phosphorus from the InP, and thereby reduce the formation of phosphorus vacancy-related defects at the interface. It is also reported that further modification of the native oxide can lead to decreased surface recombination, for example, by further oxidation or nitridation.²²³ It is quite unique that some native oxides of InP appear to form a good-quality interface with low defect density, as this is generally not the case for other III–V/oxide interfaces.

There has been quite some interest in III–V semiconductors for CMOS applications due to their high mobilities. Therefore, deposition of high- $κ$ dielectrics on III–V, often by ALD, has been investigated quite extensively. This was not only investigated for GaAs and InP, but also, for example, for InGaAs.^224,225 This is visualized in Fig. 15, where an overview of reported interface defect densities (D $i t$⁠) of Al₂O₃ and HfO₂ on GaAs, InP, and InGaAs surfaces is shown. As can be seen in the figure, D $i t$ for these interfaces is still relatively high on the order of 10¹² eV cm ^$−$2 eV ^$−$1 or above. To obtain D $i t$ lower than 10¹² cm ^$−$2 eV ^$−$1 with high- $κ$ dielectrics, typically, NH₄OH and (NH₄)₂S surface treatments are used.^198,206,210 On InGaAs, it appeared to be difficult to get a low D $i t$ using HfO₂ only. This problem may be circumvented by using Al₂O₃ interlayers^217,218,226 (not shown in Fig. 15).

An interesting observation was reported by Frank et al.,²²⁷ who investigated Al₂O₃ and HfO₂ for III–V FET applications, and found that ALD of Al₂O₃ on GaAs led to thinning of the native oxide. This was found to occur by using trimethylaluminum [Al(CH₃)₃] and H₂O.²²⁷ In the same work, deposition of HfO₂ on GaAs using HfCl₄ and H₂O did not result in thinning of the native oxide. The (partial) removal or reduction of the native oxide during deposition of the passivation layer is termed “self-cleaning” and was later also shown to occur for ALD of HfO₂ using tetrakis(ethylmethylamino)hafnium ([(CH₃)(C₂H₅)N]₄Hf) as a precursor.²²⁸ This is visualized in the x-ray photoelectron spectroscopy (XPS) spectra in Fig. 16, where it can be seen that the intensities of the oxide peaks are significantly reduced after deposition of either Al₂O₃ and HfO₂ by ALD. It is noted that various combinations of precursors with native oxides of III–V semiconductors can result in the removal of the native oxide, as discussed by Klejna and Elliot.²²⁹ 

Recently, Richard et al.²³² reported that low-frequency plasma-enhanced chemical vapor deposition (LF-PECVD) of SiN $x$ also leads to removal and reduction of the native oxides of the GaAs surfaces. Such processes may be used to better control the native oxides and improve the resulting surface passivation. An example of this is reported by Jacob et al.²³³ using the combined effects of native oxide removal and sulfurization of the surface by (NH₄)₂S, followed by further native oxide removal by deposition of LF-PECVD SiN $x$⁠. This combination resulted in up to a 29-fold increase in the PL intensity of GaAs-based nanopillars as compared to the unpassivated reference.²³³ 

Another passivation approach is epitaxially growing a layer on the semiconductor surface since this can result in an interface with a very low number of defects. This type of approach was already mentioned for germanium by using epitaxial silicon, but it has also been investigated for high- $κ$ gate dielectrics on III–V semiconductors. For these gate dielectrics, it is important that the epitaxial layer has proper conduction and valence band offsets (typically larger than 1 eV) with respect to the semiconductor.²³⁴ La₂O₃ epitaxially grown on GaAs has, for example, shown to lead to a high-quality interface with a D $i t$ of 3 $×$ 10¹¹ cm ^$−$2 eV ^$−$1.²³⁵ Another example is Gd₂O₃ on GaAs, which resulted in a D $i t$ of $∼$10¹¹ cm ^$−$2 eV ^$−$1.²³⁶ In principle, passivation by epitaxial growth can be used for any semiconductor, but there will be challenges in avoiding a lattice mismatch, which can lead to strain and relaxation, possibly leading to the formation of defects at the interface.

Although the native oxides of GaAs are typically seen as unwanted, it was demonstrated by Passlack et al.²³⁷ that deposition of Ga₂O₃ on GaAs using molecular beam epitaxy (MBE) resulted in a very low D $i t$⁠. The resulting D $i t$ values were in the upper 10¹⁰ cm ^$−$2 eV ^$−$1 for Ga₂O₃ deposited on GaAs after thermal desorption of the native oxide in UHV. At the resulting GaAs/Ga₂O₃ interface, As₂O₃ and As₂O₅ were not detected and it seems that elimination of As-oxides in general appears to be important for Fermi-level unpinning of GaAs.¹⁸⁹ However, the leakage current of FETs with Ga₂O₃ is quite high, and the usefulness of Ga₂O₃ for FET applications is limited.²³⁸ This could be improved by adding gadolinium to the Ga₂O₃, but the resulting Gd $x$Ga $0.4 − x$O_0.6 layers deposited directly on GaAs resulted in a lower quality interface. A solution was to use Ga₂O₃/Gd $x$Ga $0.4 − x$O_0.6 stacks,²³⁹ where the Ga₂O₃ serves as an interfacial layer to lead to a high-quality interface.

For passivation of InP, a similar interesting case is also using one of the native oxides, in this case phosphorus oxide (PO $x$⁠).²⁴⁰ The PO $x$ layer was capped by Al₂O₃ due to its hygroscopic nature, resulting in the PO $x$/Al₂O₃ stacks. The use of phosphorus-rich oxides is expected to reduce the formation of phosphorus vacancy-related defects at the interface, which can form due to desorption of phosphorus at elevated temperatures.¹⁰⁷ It was indeed found that using PO $x$/Al₂O₃ stacks on InP nanowires led to improved stability of the nanowires at elevated temperatures and a factor 20 increase in the PL intensity.²⁴⁰ This work was the inspiration for the use of the previously discussed PO $x$/Al₂O₃ stacks for passivation of silicon and germanium surfaces. A TEM image of an InP nanowire passivated by PO $x$/Al₂O₃ stacks can be seen in Fig. 17. Note that the native oxide is still present on the nanowire.

Over the recent years, GaN has become a mature semiconductor with applications in power electronics and LEDs.²⁷ As can be seen in Fig. 2, research on passivation of GaN picked up somewhat later than that of InP and GaAs but has now overtaken both of them in terms of the number of publications. In order to further illustrate the benefits of passivation layers in devices, we will look at the passivation of GaN-based devices in more detail. The representative GaN-based devices are high-electron-mobility transistors (HEMTs) and $μ$LEDs, whose basic structures are schematically shown in Fig. 18.

GaN-based power devices, such as AlGaN/GaN HEMTs, can suffer from challenges, such as current collapse and threshold voltage instability, which are attributed to charge trapping at interface and surface states.^241–243 In order to mitigate these problems, several passivation approaches have been used to reduce the number of surface states. Similar as for the previously discussed semiconductors, Al₂O₃ and SiN $x$ were some of the main investigated passivation layers.^242,243 It was shown that both Al₂O₃ and SiN $x$ passivation layers could reduce current collapse.²⁴³ However, using SiN $x$ can lead to large leakage currents;²⁴² on the other hand, using Al₂O₃ can result in threshold voltage instability.²⁴³ The use of HfO₂ often resulted in high leakage currents or threshold voltage instability;^242,243 thus, its application for GaN-based HEMTs does not appear straightforward. Nevertheless, GaN devices with good characteristics have been obtained using passivation layers, often in conjunction with interface control layers, or through the use of stacks.²⁴³ In particular, AlN has shown to suppress current collapse and reduce the dynamic ON-resistance at high drain-bias switching conditions, demonstrating effective passivation of GaN.²⁴⁴ AlN/SiN $x$ stacks could retain effective passivation, even after high temperature processing.²⁴⁵ Gao et al.²³⁰ have compared stacks of Al₂O₃/SiN $x$ and NiO $x$/SiN $x$ with single layer SiN $x$ as combined gate dielectric and passivation layers for GaN-based HEMTs. They reported that both stacks were able to increase the breakdown voltage, reduce the leakage current, and reduce current collapse as compared to the single layer SiN $x$⁠. This was attributed to a lower D $i t$ achieved by these stacks by minimizing damage at the (Al)GaN surface.

GaN-based $μ$LEDs, such as InGaN/GaN $μ$LEDs, typically suffer from defects at the sidewalls, which can lead to nonradiative recombination. It has been observed that this is more severe for smaller $μ$LED devices,²⁴⁶ underlining the importance of surface passivation with continued device scaling. In order to mitigate this problem, several passivation treatments have been attempted, including the use of chemical treatments and/or dielectric materials.¹⁹⁷ In a similar vein as for the HEMTs, some of the used dielectrics include Al₂O₃, SiO₂, and SiN $x$⁠. Recently, Son et al.²³¹ compared these three different passivation layers for InGaN/GaN-based $μ$LEDs. The passivation layers also acted as an antireflection coating in this case. They showed that the SiO₂ and Al₂O₃ were the most effective passivation layers for reducing sidewall defects. The reported PL efficiencies of the $μ$LEDs were 25.1% (SiO₂), 21.1% (Al₂O₃), 15.4% (SiN $x$⁠), and 10.5% (no passivation).²³¹ 

Defects occurring at the surfaces and interfaces of semiconductors can significantly hamper the development and performance of semiconductor devices and should, therefore, be passivated. Semiconductor surface passivation focuses on obtaining high-quality interfaces with low interface defect density. For silicon, it is relatively straightforward to obtain a high-quality interface, and the remaining defects can typically be further passivated by hydrogen. For germanium and III–V semiconductors, it is often significantly more challenging to form a high-quality interface, and the role of hydrogen passivating the remaining defects occurring at these interfaces is less clear.

In general, the approaches for surface passivation of various semiconductors are highly similar and focus on interface management by removal of the native oxide, followed by surface treatments and/or deposition of passivating (inter)layers, while avoiding the formation of defects. When exploring surface passivation schemes for a novel semiconductor, it can be beneficial to use known passivation schemes of another semiconductor. For example, passivation schemes involving Al₂O₃, SiN $x$⁠, HfO₂, and PO $x$/Al₂O₃ have already been investigated on silicon, germanium, and III–V semiconductors. However, due to the high complexity of the interactions between the semiconductor, the passivation scheme, and their interfaces, this can lead to varying degrees of success. Therefore, it is recommended to tailor the passivation schemes to the semiconductor and the application. These types of investigations will allow for the toolbox of semiconductor surface passivation to be further extended and understood.

In the near future, it is likely that continued advances in semiconductor devices will lead to the requirements of passivation schemes to become more stringent. This is likely exacerbated by the current trends of continuous scaling of semiconductor devices and a switch to 3D structured devices. To fulfill these more stringent requirements, the use of stacks of passivation layers is likely to become more commonplace since this provides additional control over the properties of a passivation scheme as compared to the use of a single passivation layer. Furthermore, it is not a given that the currently used passivation approaches are directly compatible with 3D structured devices. Continued research is, therefore, required, in order to achieve proper passivation of semiconductor surfaces with highly stringent requirements. This will allow for further improvement of performance, stability, and reliability of current and future semiconductor devices.

This work was supported by the Netherlands Organization for Scientific Research (NWO) through the Gravitation/Zwaartekracht program “Research Centre for Integrated Nanophotonics” (Grant No. 024.002.033).

The authors have no conflicts to disclose.

Roel J. Theeuwes: Conceptualization (equal); Investigation (equal); Visualization (equal); Writing – original draft (equal). Wilhelmus M. M. Kessels: Funding acquisition (equal); Supervision (equal); Writing – review & editing (equal). Bart Macco: Funding acquisition (equal); Supervision (equal); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.