Morphological and electrical characterization of gate recessed AlGaN/GaN high electron mobility transistor device by purge-free atomic layer etching

Modern microelectronic components for high-power and high-frequency applications based on III–V compound semiconductors offer high breakdown voltage [GaN: 5 MV/cm (Ref. 1) and AlN: 15 MV/cm (Ref. 2)] at low specific on-resistance.^{3, 4} However, it requires reliability and reproducibility of production processes. For higher frequencies (5 GHz and beyond) and more cost-efficient application for consumer electronics, smaller structure sizes are needed. Transistors based upon nitride semiconductors, the heterojunction field effect transistors (HFETs) or high electron mobility transistors (HEMTs), are used. A heterojunction of an AlGaN barrier to a GaN buffer layer is formed by two-dimensional electron gas (2DEG)^{5, 6} with high electron mobility (i.e., 2000 cm² V⁻¹ s⁻¹ at 300 K)⁷ and high carrier concentration (∼1 × 10¹³/cm²).^7,8 These superior properties make the HEMT a promising candidate for high-frequency (i.e., 151 GHz)⁶ and high-voltage power switching devices.^8–10 The AlGaN/GaN HEMT is intrinsically normally-on and, hence, operates in the depletion mode (D-mode).^11,12 Practically, a normally-off property is required, i.e., for better integration into the established MOSFET circuit design. Shifting the threshold voltage (V_th) toward positive values is called an enhancement mode (E-mode).^{11, 12} It can be realized in several ways, for example, the treatment of the gate with fluorine plasma,¹¹ a p-GaN gate structure,¹³ or by recessing the gate contact into the AlGaN barrier by dry etching.^12,14–18 The recess of the gate contact brings the gate closer to the 2DEG, which increases the gate capacitance and reduces the polarization field at the interface. Thus, the electric field of the gate is switching the 2DEG off at lower gate voltages or the 2DEG is even turned off at zero potential at the gate. AlGaN/GaN is usually dry etched by Cl₂/BCl₃ etching chemistry and Ar ions for the bombardment using a reactive ion etching (RIE) tool.^19–21 A precise controlled etching rate is necessary to etch the gate into the AlGaN barrier on a nanometer scale. Deviations from the desired etching depth result in over- or underetching, which has a high impact on the V_th shift. The etching rate should be stable over time. High controllability, uniformity, and repeatability are necessary for low damage and hence satisfying reliability of the devices. Plasma etching can cause surface and subsurface damage >20 nm depth, generating lattice defects, nonstoichiometric surface, vacancies, interstitials, and polymeric film deposition by chemical reactions.^19,20,22,23 These damages degrade the device performance, for instance, by increasing sheet resistance (R_Sh), reducing electron mobility, and creating interface traps or donor levels.^19,20,22,23 Some etching defects can be recovered by thermal treatment after the etching process.^19,20,24,25 Reducing the plasma induced damage is indispensable for realizing gate recess etching while keeping device performance. For continuous etching process using RIE, lowering the plasma source or electrode power is one option to reduce the damage, but it is a restricted one.

Atomic layer etching (ALE) was developed for achieving a precise the precise etching rate on the subnanometer scale and reducing the plasma induced damage. It is a sequential cyclic process, whose key feature is to split a continuous etching process (RIE) into at least two separate steps. In the first step, the so-called modification step, a thin surface layer, ideally on an atomic scale, is modified by a chemical precursor. In the second step, the so-called removal step, this thin layer can be easier removed than the unmodified surface below by a physical impact. Ideally, both steps should be self-limiting.^19,22 In this way, a specific etch per cycle (EPC) can be accurately adjusted, which increases the controllability of the ALE process. For gate recess on an AlGaN/GaN heterostructure using chlorine chemistry, the ALE process could be described as follows. In the first step, the surface will be modified by Cl₂/BCl₃ plasma. This chlorination of the surface produces volatile GaCl_x and AlCl_x species due to chemisorption. In the following removal step, Ar ions are accelerated toward the surface with low energy to remove the modified layer.^19,26–28

In this study, the threshold voltage shift of AlGaN/GaN HEMTs is studied by increasing the gate recess etching depth using an ALE process without purge in between the steps, which enables, in principle, shorter cycles. A morphological investigation of the surface roughness and the etching depth is realized by atomic force microscopy (AFM). Manufactured HEMTs were electrically characterized by IV and CV measurements.

The HEMT devices were fabricated on an AlGaN/GaN heterostructure grown by metal-organic vapor phase epitaxy on 4-inch sapphire substrates (Fig. 1). These heterostructures consist of a 1.9 μm thick semi-isolating GaN buffer layer, a 24 nm thick Al_0.25Ga_0.75N barrier layer, and a GaN cap-layer of 1.5–2 nm. All lithographical steps were performed using a photoresist layer (AZ 5214) exposed in direct writing laser lithography. Device isolation was carried out by etching into the buffer layer using an SI500 RIE from Sentech. Due to the longer duration of the ALE process, a patterned photoresist becomes hardened. For this reason, a 50 nm silicon dioxide hard mask was deposited by plasma enhanced chemical vapor deposition. The hard mask was structured by wet chemical etching using a buffered hydrofluoric acid solution (7:1) with a patterned photoresist. Recess etching was performed in a SI500 PEALE from Sentech. For the determination of the threshold voltage shift, three transistors with recess depths of 7, 14, and 21 nm were etched. Impurities and the native oxide layer were removed by a pretreatment of accelerated Ar ions out of a plasma prior to the recess etching. The gate recess was driven by means of repeated ALE cycles without purge steps in between. The sample temperature was set to 20 °C. In the first step, a chemical modification was performed by Cl₂/BCl₃ plasma (60/10 sccm) for 5 s. The power of the inductively coupled plasma (ICP) source was set to 300 W and the pressure to 7.5 mTorr for this step. In the following removal step, Ar ions are generated with 300 W ICP power at a pressure of 5.25 mTorr and accelerated by a self-bias fixed at −25 V by a time span of 50 s. The self-bias was adjusted to the point where no sputtering of the AlGaN/GaN material is observed. After each step, the plasma was switched off for a delay time of 5 s. A precise adjusted EPC of 0.5 nm/cycle was achieved, which corresponds to 1 unit cell in the c-direction with c = 5.185 Å.²⁹ Contact metals were deposited by e-beam evaporation. Source-drain ohmic contacts consist of a Ti (15 nm)/Al (80 nm)/Ni (20 nm)/Au (100 nm) multilayer metal stack annealed using rapid thermal annealing (RTA) at 800 °C for 300 s in N₂ ambient. A Ni (20 nm)/Au (100 nm) metal stack was chosen for the Schottky gate contact, and a postmetallization RTA was performed at 400 °C for 300 s in the N₂ atmosphere. The HEMTs have a gate length of 5 μm, a gate-source spacing of 5 μm, a gate-drain distance of 5 μm, and a gate width of 50 μm.

A Park Systems NX 10 atomic force microscope with Olympus AC160TS cantilevers was used to evaluate surface morphology in the noncontact mode. For the root-mean-square (RMS) surface roughness, a 5 × 5 μm area was scanned with 512 × 512 pixels for all samples. RMS was determined with Gwyddion.³⁰ The ALE recess etching depths were determined by measuring the edge height in a 10 × 10 μm (256 × 256 pixel) scan.

Figure 2 reveals the AFM measurements for the etched and unetched samples. Here, the etching depths were determined by subtracting the height at the top area from the height at the bottom area. Corresponding to the ALE cycle of 15, 30, and 44, the following depths (7.3 ± 0.5), (13.6 ± 0.5), and (21.0 ± 0.5) nm were determined. Figure 2(e) shows a 3D view of the steep etched edge for the 33 cycle recess. For all three ALE recesses, an EPC of ∼0.5 nm was achieved. This constant etch per cycle enables precise control of the gate recess etching depth and the channel engineering.

An important metric to analyze the surface morphology is the root-mean-square surface roughness. Figures 2(a)–2(d) compare the 5 × 5 μm² AFM scans of an initial unetched surface with the ones for the three different recess etching depths. It shows the top view of the scanned area. All scans are leveled to the zero mean value, and the same color bar scale is applied. White particles (out of the scale) are contaminations from sample dicing and were masked for roughness determination. The ALE gate-recessed samples for each etching depth exhibit an RMS value of 0.3 nm [Figs. 2(b)–2(d)], similar to the unrecessed surface of 0.3 nm [Fig. 2(a)]. For all three etching depths, no significant increase in the surface roughness was observed, which is attributed to the separation of the chemical and physical step during the ALE cycle. The consistent isotropic chemical modification in the first step and the following self-limiting removal (without sputtering the unmodified layer) at the second step keeps the smoothness for every etched layer. In comparison to a continuous Cl₂/BCl₃/Ar etching plasma, separation into two independent steps minimizes the acceleration and injection of Cl₂ and BCl₃ ions into the surface. Furthermore, low surface roughness for all different etching depths indicates continuous low damage etching through the Al_0.25Ga_0.75N barrier and demonstrates the reliability of the presented ALE process.

The processed HEMTs were characterized by capacitance voltage (CV) and current voltage (IV) measurements. Figure 3(a) shows the gate capacitance for a gate voltage sweep from +0.5  to −8 V at 100 kHz. According to the reduction in barrier thickness, the capacitance at 0 V gate bias increases for a higher ALE cycle number, as expected. All devices exhibit a sharp decrease in capacitance when 2DEG is depleted. The absolute value of the gate bias required to deplete the 2DEG is largest for the HEMT without ALE gate recess etch and decreases with increasing ALE cycle number. After 44 cycles of ALE, the 2DEG is already depleted at zero gate voltage, changing the behavior of the HEMT from depletion to enhanced mode (normally-off). The threshold voltage V_th was extracted from CV characteristics at C_p being half of the maximum capacitance. Figure 3(b) shows a linear relationship between V_th and ALE cycle count. The largest negative V_th of −(3.38 ± 0.04) V was observed for the unetched HEMT, while 44 ALE cycles lead to a V_th of +(0.09 ± 0.02) V.

The transfer characteristics [Fig. 4(a)] reflect the behavior of the CV measurements, with increased etching depth V_th shifting toward positive gate bias. Simultaneously, the drain saturation current I_sat decreases [Fig. 4(b)]. Due to the thinner barrier layer, strain and, thus, polarization is lowered, which leads to a reduced sheet carrier density of the 2DEG below the gate contact. Thus, the channel resistance increases, and I_sat is reduced from (234 ± 22) mA/mm for the unetched HEMT to <1 mA/mm after 44 ALE cycles. In addition, the drain current in the off-state of the HEMTs increases with increased etch depth. The off-state drain current is limited by the gate leakage current that rises due to the thinning of the AlGaN barrier by ALE.

AlGaN/GaN HEMTs with three different gate recess etching depths of (7.3 ± 0.5), (13.6 ± 0.5), and (21.0 ± 0.5) nm were processed using the atomic layer etching technique. An ALE process without purge was developed consisting of repeated cycles where Cl₂/BCl₃ plasma modifies the surface through chemisorption and which was removed by low energy Ar ions. For each recess, an EPC of ∼0.5 nm was achieved, similar to one unit cell in the c-direction, showing the precision and controllability of the developed ALE process. The smoothness of the unetched reference could be kept constant over etching depth, resulting in an RMS roughness of 0.3 nm for all samples.

A linear relationship between V_th and etch depth was determined from the fabricated HEMT devices. A 20 nm deep recess is required to achieve the enhancement mode in these devices. However, a deeper gate recess leads to increased channel resistance, lower saturation current, and higher gate leakage. To omit the high leakage current, an additional gate dielectric could be deposited. Additionally, a trade-off between leakage, saturation current, and V_th has to be found.

The results from electrical and morphological measurements confirm the great potential of recess etching using a purge-free ALE process with precise EPC for contact and channel engineering of AlGaN/GaN HEMTs.

This work was financially supported by the Fraunhofer Internal Programs under Grant No. Attract 079-600865, the European Regional Development Fund, and the Saxonian Government (Project: ALEStar; Grant No. SAB: 100402927).

The authors have no conflicts to disclose.

Christian Miersch: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Sarah Seidel: Data curation (equal); Formal analysis (equal); Visualization (equal); Writing – original draft (supporting); Writing – review & editing (supporting). Alexander Schmid: Data curation (equal); Formal analysis (equal); Visualization (equal); Writing – original draft (supporting); Writing – review & editing (supporting). Thomas Fuhs: Data curation (equal); Funding acquisition (lead); Project administration (lead); Supervision (lead); Writing – review & editing (equal). Johannes Heitmann: Data curation (equal); Funding acquisition (equal); Writing – review & editing (equal). Franziska C. Beyer: Funding acquisition (lead); Project administration (lead); Supervision (lead); Writing – review & editing (supporting).

The data that support the findings of this study are available from the corresponding author upon reasonable request.