Bias-pulsed atomic layer etching of 4H-silicon carbide producing subangstrom surface roughness

The legacy of electronic devices is one of rapid downscaling and increasing precision. One of the key technologies for this industry is atomic layer etching (ALE), which is a cyclical process that removes single layers of atoms from a substrate with each cycle. ALE is mainly employed in chip manufacturing, but it is also valuable in any application requiring precise and smooth etching.

ALE can be described as a two step process. First, the interfacial layer of atoms is chemically modified in a way to make them more weakly bound to the rest of the substrate. Second, the chemically modified layer of atoms is removed in a way that minimally interacts with the substrate below.^1,2 While Si ALE has seen the most development and process variety, ALE has also been demonstrated for a host of various relevant materials.^1–3 

4H-SiC (referred to as SiC hereon) is the most common polytype of SiC and is used in a variety of electronic and optical devices, most notably in power electronics,^4–6 but also in epitaxy, integrated optics,^7,8 and quantum technology as a host to optically active, point defect qubits.^9–13 Moreover, the predominant etching technique for SiC, inductively coupled plasma-reactive ion etching (ICP-RIE), often causes crystal damage and surface roughness that impedes optical and electrical performance and must be repaired after etching.^14,15 Lee et al. developed what they deemed “quasi-ALE” for SiC as it resulted in ALE-like smoothness and slow etching but was not self-limiting in nature.¹⁶ 

Here, we report the first instance of ALE in SiC using plasma at room temperature (substrate temperature = 20  $°$C) and Ar and Cl $2$ chemistry in an Oxford Instruments PlasmaPro 100 Cobra system. Unlike most ALE processes in which the flow of the constituent gases is modulated in time as to control chamber chemistry, this work presents bias-pulsed ALE, which only pulses the DC bias (RIE power) to achieve ALE. This enables far shorter duration cycles than conventional ALE; we report a reduction of more than an order of magnitude in the ALE cycle period relative to conventional ALE processes. This novel process is studied as a function of Cl $2$ flow, RIE power, and step lengths. The thresholds for incomplete layer removal, atomic layer etching, and sputtering are reported, along with single SiC dimer (i.e., the Si-C doublet layer) removal, $0.83±0.08$ Å RMS surface roughness (R $q$⁠), and 99% ALE synergy, which is a metric that gauges the ideality of an ALE process.

Semi-insulating 4H-SiC substrates from MSE Supplies LLC were used in this study. A simple step pattern was translated to the Si-face of the substrates with an AZ5214E photoresist, which was exposed in a Karl Suss MJB3 contact aligner equipped with a 320 nm, 9 mW/cm $2$ light source and then developed with an AZ 917 MF developer. The lithographically patterned SiC pieces were cleaved into $2×2$ mm $2$ substrates, then bonded with an alumina wafer using Crystalbond 555, and etched in an Oxford Instruments PlasmaPro 100 Cobra system. All experiments in this work were performed at room temperature with only Ar and Cl $2$ gas mixtures.

Chamber pressure and Ar flow were kept constant at 7 mTorr and 100 sccm, respectively, and Cl $2$ flow was varied from 0 to 40 sccm. Both gas flows were kept constant during all process steps. ICP power was kept at 1000 W, and RIE power was varied from 0 to 40 W.

The maintenance of gas flow rates throughout the ALE process eliminated the typical requirement for gas purging steps. Instead, the etch was characterized by the duty cycle of the RIE power (i.e., “bias-pulsing”); surface modification and ion bombardment occur when it is off and on, respectively. As such, the first ALE step had the RIE power off and the second step turned the RIE power on for the entirety of the step duration. These two steps comprise what is commonly referred to as an ALE cycle. For an etch rate metric, an etch per cycle (EPC) was reported to characterize the speed at which the process occurred. EPC was calculated by measuring the etch depth for a processed substrate and dividing it by the total number of cycles ran for that sample. Every substrate in this study was etched for 200 cycles unless otherwise noted. The etch depth and RMS surface roughness were measured with $20×20μ$m $2$ and $1×1μ$m $2$ scans, respectively, using an Asylum MFP3D atomic force microscope equipped with a diamondlike carbon tip. Power spectral density (PSD) scans were obtained with $90×90μ$m $2$ AFM scans taken on the same instrument and were analyzed according to the procedures detailed in the supplementary material.¹⁷ 

Figure 1 illustrates the ALE steps developed for this work. Note that both Ar and Cl $2$ are flowing continuously at a constant rate throughout both cycles; only the RIE power distinguishes the steps. Step 1 involves chemically modifying the surface with ground state, electronically excited, and ionized Cl $2$ as well as Ar metastables and ions. This step chlorinates the surface atoms and lowers their binding energy with respect to the substrate surface. It also amorphizes the surface and allows for the formation of various chlorine-bearing compounds.¹⁸ This enables step 2, in which accelerated and energetic radicals remove the modified surface layer.

Conventional ALE processes often pulse gases to better control the etch chemistry. In this work, only the DC bias (RIE power) is pulsed on and off. Therefore, the pulse durations are referred to as t $on$ and t $off$⁠, the time the RIE power is on and off, respectively, and the total time for a cycle is equal to t $on$ $+$ t $off$⁠.

There is no need to purge the chamber after each step because the gases are flown continuously. The result is far shorter duration cycles and, therefore, faster processing. ALE processes often have etch cycle periods approaching a minute and beyond.^2,19–26 The ALE process presented here has a total cycle time of 6 s.

After an etch was performed, multiple scans were obtained of the step at different points at least 100  $μ$m apart on the sample. A height was extracted by subtracting the height at the top of the step by the height at the bottom of the step. EPC values were calculated by averaging these measurements together and dividing that by the total number of cycles for the etch. Figure 1(b) displays a drawing of the step pattern printed on each substrate. The dashed line indicates the region that would be scanned for a step measurement. Figure 1(c) is an example line scan of a step measured in this study.

Figure 2 summarizes measurements of various relevant processes. Figure 2(a) illustrates the dependence of the SiC EPC on the percentage of Cl $2$ in the chamber. The onset of saturation is observed when the Cl $2$ flow rate is >15% of the total. This agrees with past works, where the chemical modifier in the ALE process increases the overall etch rate until the surface layer is modified completely.^1,2,16 Figure 2(b) displays a study of the effect of RIE power. A threshold at 6 W is observed, which indicates that the number density of Ar ions or metastables is subcritical or that the mean Ar ion energy is insufficient to remove the modified surface layer. Beyond this threshold, a linear relationship exists between EPC and RIE power.

Figures 2(c) and 2(d) show the effect of changing t $off$ (surface modification) and t $on$ (ion bombardment). The gray dashed lines indicate the etch rate corresponding to the removal of a single SiC dimer layer. The variation of the SiC EPC with respect to t $off$⁠, presented in Fig. 2(c), demonstrates that the DC bias must be zero for 2 s or more when t $on$ is 4 s. This is equivalent to requiring that the DC bias duty cycle be $≤$66.7%. Though the surface is likely amorphized during the t $off$ step, it appears that the surface modification is limited to the interfacial SiC dimer layer. The dimer layer is the expected self-limiting feature for this etch because the Si-C dimer bond energy exceeds that of the dimer-to-dimer (Si-C to Si-C) bonding.²⁷ This implies that it is energetically more favorable to remove an entire dimer rather than an adatom or monomer from the surface and scientifically supports the single dimer layer self-limiting nature of this etch. The increase in EPC for the shorter t $off$ times is expected because this is approaching the limit of continuous ICP-RIE etching. Figure 2(d) plots the relationship between EPC and t $on$⁠. There are three regimes indicated on the plot: (I) incomplete surface layer removal, (II) single SiC dimer removal, and (III) multilayer removal or sputtering. It is likely that (III) is the result of additional surface atoms being chlorinated and then removed during the etch step after the initial dimer layer is already removed. Although this study did not find an ALE window with respect to RIE power, it did observe such a window with respect to t $on$⁠.

RMS surface roughness (R $q$⁠) is also a vital metric for gauging the utility of this ALE process for surface-dependent applications. Figure 3 compares AFM scans of the surface before and after ALE etching. The data are presented with median plane subtraction in order to remove stage tilt. Both 3D maps share the same color bar. Figure 3(a) corresponds to the surface before etching, with R $q$ = $4.91±0.24$ Å, and Fig. 3(b) corresponds to the surface after etching with 1000 W of ICP power, 10 W RIE power, 100 sccm Ar, 40 sccm Cl $2$⁠, t $off$ = 8 s, and t $on$ = 4 s for 200 cycles. The resulting surface had R $q$ = $0.83±0.08$ Å.

Note that both scans have ∼1 µm pitch ridges. These are the result of the optical polish applied to the substrate wafer during manufacturing. These polishing-produced ridges are substantially reduced by the ALE process. These results indicate that this process could be used to smooth SiC wafers beyond conventional industrial polishing. It is also a promising candidate for fabricating devices that are sensitive to surface-proximal damage and amorphization.

Power spectral density (PSD) is a more consistent method to judge surface roughness features that span various spatial frequencies.²⁸  Figure 3(c) plots the PSD of two 90 $×$ 90 μm $2$ scans taken at the same area on the same substrate before and after etching. The log-log plotted line scans were aligned perpendicularly to the 1 μm ridges. The black (dotted) and red (solid) plots correspond to the substrate before and after etching, respectively. Note that while the same features are found at steps of $1μ m − 1$⁠, they are considerably reduced after the etch, always more than an order of magnitude. For more details on how this PSD was analyzed and obtained, please refer to the supplementary material.¹⁷ 

This study demonstrates atomic layer etching of 4H-SiC using Ar and Cl $2$ based chemistry. The process utilizes a bias-pulsing method that reduces processing time by an order of magnitude relative to previous ALE processes while maintaining etch performance. The effects of Cl $2$ rate, RIE power, and step duration were studied with respect to EPC and RMS surface roughness. R $q$ of $0.83±0.08$ Å and an etch synergy of 99% were demonstrated, making this process viable for both etching and smoothing SiC.

The support of this work by Oxford Instruments is gratefully acknowledged. Special thanks go to Karthick Jenganathan (UIUC Holonyak Micro and Nanotechology Laboratory) and Kathy Walsh (UIUC Materials Research Laboratory) for maintaining the ALE and AFM instruments used in this paper. We also thank David Graves (Princeton University and Princeton Plasma Physics Laboratory) for helpful discussions. Additional support was provided by Q-NEXT, part of the U.S. Department of Energy, Office of Science, National Quantum Information Science Research Centers (D. D. A. and F. J. H.) and the U.S. Department of Energy, Office of Basic Energy Sciences, Materials Science and Engineering Division (N. D.). Y. T. was supported by an Internationalization Fellowship (No. CF20-0475) from the Carlsberg Foundation.

The authors have no conflicts to disclose.

J. A. Michaels: Conceptualization (equal); Data curation (lead); Formal analysis (lead); Investigation (lead); Methodology (equal); Validation (equal); Visualization (lead); Writing – original draft (lead); Writing – review & editing (equal). N. Delegan: Conceptualization (equal); Formal analysis (supporting); Methodology (equal); Visualization (supporting); Writing – original draft (supporting); Writing – review & editing (equal). Y. Tsaturyan: Conceptualization (equal); Formal analysis (supporting); Methodology (supporting); Visualization (supporting); Writing – review & editing (equal). J. R. Renzas: Conceptualization (equal); Funding acquisition (lead); Project administration (equal); Resources (equal); Supervision (equal); Validation (supporting); Writing – review & editing (equal). D. D. Awschalom: Resources (equal); Supervision (equal); Writing – review & editing (supporting). J. G. Eden: Resources (equal); Supervision (equal); Writing – review & editing (equal). F. J. Heremans: Conceptualization (equal); Funding acquisition (supporting); Project administration (equal); Resources (equal); Supervision (lead); Visualization (supporting); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.