The design of β-Ga2O3-based modulation-doped field effect transistors is discussed with a focus on the role of self-heating and resultant modification of the electron mobility profile. Temperature- and doping-dependent model of the electron mobility as well as temperature- and orientation-dependent approximations of the thermal conductivity of β-Ga2O3 are presented. A decrease in drain current was attributed to a position-dependent mobility reduction caused by a coupled self-heating mechanism and a high electric-field mobility reduction mechanism. A simple thermal management solution is presented where heat is extracted through the source contact metal. Additionally, it is shown that an undesired secondary channel can form at the modulation-doped layer that is distinguished by an inflection in the transconductance curve.
Monoclinic β-Ga2O3-based transistors possess fundamental electronic properties that are advantageous for high power devices.1 A number of these properties derive directly from the wide bandgap of β-Ga2O3 (Eg = 4.8 eV) including an exceptionally high electric breakdown field (approximately 8 MV/cm).2 The high breakdown field allows for the design of a lateral transistor with a short channel that can withstand a high critical field. The short channel design lowers the switching loss and, also, lowers the on-resistance, which reduces the conduction loss.3 Additionally, the short channel allows the high-voltage switch to operate at high frequency (>1 MHz) and, thus, enables a system design with smaller (size and weight) passive circuit components.4
A lateral metal-semiconductor or metal-oxide-semiconductor field effect transistor is typically based on an n-type doped channel. At carrier concentrations greater than 1 × 1018 cm−3, the mobility of β-Ga2O3 is limited to approximately 50 cm2/V s due to impurity scattering.5 In contrast, at a carrier concentration of 2.5 × 1016 cm−3, a mobility of β-Ga2O3 of 184 cm2/V s has been reported—primarily limited by polar optical phonon scattering.6 This provides the motivation for a modulation-doped design where donors within the (AlxGa1−x)2O3 barrier accumulate in a triangular potential well in the undoped Ga2O3 crystal at the (AlxGa1−x)2O3/Ga2O3 interface. An (AlxGa1x)2O3 spacer layer physically separates the dopant atoms from the electrons in the conductive channel, which reduces impurity scattering and, thus, improves electron mobility.
With proper design, conduction predominantly occurs via the dense two-dimensional electron gas (2DEG) that forms in the potential well. Nevertheless, a deleterious secondary channel may form at the modulation-doping location in the (AlxGa1x)2O3 barrier. See supplementary material23 for general design rules for an optimal formation of the 2DEG. The supplementary material23 focuses on mitigating three limitations related to current deposition technology involving the aluminum content in (AlxGa1−x)2O3, modulation-doping concentration, and the persistent tail of dopant atoms. Below, it is shown that residual charge in the (AlxGa1−x)2O3 barrier manifests as a secondary inflection in the transconductance curve.
This primary aim of this article is to investigate the coupled relation of on-state self-heating and spatially dependent mobility reduction, and the resultant alteration of the forward bias response. The mobility decreases significantly at elevated temperature and the low thermal conductivity of β-Ga2O3 results in self-heating of the device at moderate current density. Approximations to the mobility and thermal conductivity of β-Ga2O3 are presented that can be readily implemented in a Technology Computer-Aided Design (TCAD) simulation environment. It is shown that self-heating and the electric-field dependence will significantly alter the cross-sectional mobility profile. Significant self-heating can result in a negative differential conductance in the drain current response to increasing drain voltage.
A series of electrothermal simulations, via the Silvaco TCAD environment, were conducted for a modulation-doped (AlxGa1−x)2O3/Ga2O3 structure to provide insight into the device current-voltage relationships as well as the cross-sectional profiles of current density, mobility, and temperature.
A. Thermal conductivity and mobility models
An accurate description of the temperature dependent parameters is necessary for the simulation of a transistor based on Ga2O3, which suffers from self-heating related to its low thermal conductivity. For application to a TCAD simulation, the thermal conductivity model given in Mu et al.7 was fit to a power-law thermal model given by
with the parameters listed in Table I.
(W/cm K) .
(W/cm K) .
Ma et al. developed a model of mobility of Ga2O3 that accounted for several scattering mechanisms.8 The Ma mobility model, based on the Boltzmann transport equation via the relaxation-time approximation solution, requires two separate integrations. To introduce a temperature and donor dependent model into the device simulation, the Boltzmann model of Ma et al. was fit to the Arora low-field mobility model9 with a structure in the Silvaco TCAD environment given by
with fitting parameters given by μ1 = 1.679 38 cm2/V s, μ2 = 264.557 cm2/V s, α = − 0.116 259, β = − 2.292 57, γ = 2.644 26, and Ncrit = 4.294 47 × 1018 cm−3.
Figure 1(a) displays the calculated mobility of the Arora model compared to the calculated Ma model and the specific scattering mechanisms defined in the Ma model. Figures 1(b) and 1(c) display the Arora calculated mobility as a function of dopant density and temperature. The Arora model replicates the Ma model, which predicts a transition from polar optical phonon scattering as the limiting mechanism at a low donor level to impurity scattering as the dominant mechanism limiting the mobility, above 200 °K, at a high donor level.
B. Device structure
The base simulation structure consists of 20 nm Atomic Layer Deposition (ALD) Al2O3, 30 nm (Al0.25Ga0.75)2O3 with a background donor concentration of 1 × 1017 cm−3 and modulation doped at 4 × 1019 cm−3 with a Gaussian distribution with a characteristic length of 0.5 nm that peaks at 4 nm from the layer bottom, 200 nm Ga2O3 with a background donor concentration of 1 × 1015 cm−3, and a 200 μm Ga2O3:Fe substrate with a thermal boundary resistance of 0.001 cm2 K/W. The source and drain contacts are 50 μm in length and composed of 20 nm Ti and 300 nm Au. The gate contact is 5 μm in length and composed of 20 nm Ni and 300 nm Au. The source to gate spacing is 3 μm and the gate to drain spacing is 12 μm. The remaining structure consists of Si3N4.
As shown in Fig. 2(a) heatsink, with a temperature dependent thermal conductivity similar to ceramic poly-AlN, is optionally added. The heatsink is 50 μm in length and ends 5 μm from the edge of the source metal. The heatsink is separated by 50 nm of Si3N4 from the source metal. The heatsink has a thermal boundary resistance of 0.001 cm2 K/W and the Ga2O3:Fe substrate is thermally isolated.
A. Electrothermal simulation with thermal contact to substrate base
A simulation of the device structure was conducted, with a thermal contact to the substrate base, as described in Sec. II. The drain current and the peak temperature as a function of forward drain bias are displayed in Fig. 3(a). At a drain bias above 3 V, the temperature of the device rapidly increases. Additionally, above 7 V, a negative differential conductivity is observed. The increase in temperature relative to the increase in power corresponds to a device thermal resistance (Rth = ΔT/PD) of 167 mm K°/W at 10 V (and 359 °K).
Figure 3(b) displays the drain current and peak temperature as a function of gate bias for a drain voltage of 5 and 10 V. At a drain voltage of 5 and 10 V, the peak device temperature plateaus at approximately 325 and 385 °K, respectively. At a large positive gate bias, the gate minimally impacts the channel, which behaves similar to a resistor. Moving from a drain voltage of 5–10 V corresponds to a 47% increase in drain current but a 132% increase in temperature.
Figure 4 compares the log current density, x-component (direction from source to drain) of the mobility, and temperature at a fixed drain current (of Vd = 10 V). The left-column corresponds to the near complete depletion of the channel (at Vg = − 4 V), center-column corresponds to the point of initial depletion (starting at the drain side of the gate edge) in the channel (at Vg = 0 V), and right-column is the transitional point of depletion of the (Al0.25Ga0.75)2O3 barrier (at Vg = 2 V) in Fig. 4.
In Figs. 4(d) and 4(e), the reduction in mobility at the drain side of the gate edge is caused by the peak in x-component of the electric field as predicted by the high-field dependent mobility model. This causes a local increase in resistance, which similarly causes an increase in Joule heating and a corresponding peak in temperature at the drain side of the gate edge. In Fig. 4(a) (at Vg = − 4 V), it is seen that the total current is low; thus, the Joule heating throughout the channel is low and the overall temperature increase in the structure is minimal as observable in Fig. 4(g).
In contrast, in Fig. 4(b) (at Vg = 0 V), a significant current is flowing in the channel, which causes Joule heating along the length of the channel as well as a relatively higher increase in heating at the drain edge of the gate (due to the high electric-field induced mobility reduction). This generated heat sharply increases the temperature at the drain side of the gate edge in the channel [Fig. 4(h)]. A temperature gradient exists moving away from the gate edge but the temperature in the surrounding structure is sufficient to cause an appreciable reduction in the mobility in the corresponding region [Fig. 4(e)].
The transitional point of depletion of the (Al0.25Ga0.75)2O3 barrier (at Vg = 2 V) reveals a small yet discernable secondary current flow in (Al0.25Ga0.75)2O3 barrier near the location of the modulation doping [Fig. 4(c)]. Additionally, at this gate bias, the electric field from the gate has essential no interaction with the primary channel. Hence, the potential well below the (Al0.25Ga0.75)2O3/Ga2O3 interface effectively acts as a high-conductivity resistor. The manifests as heating along the entire channel that creates a non-localized heating profile [Fig. 4(i)] and a relatively uniform reduction in mobility in the Ga2O3 [Fig. 4(f)].
B. Comparison to isothermal simulation
A simulation was conducted of the same device structure except thermal heating is neglected, that is, the device is held at 300 °K. Examination of the mobility cross section, in Fig. 5(b), reveals a sharp decrease in mobility at the drain side of the gate edge—and a smaller decrease at the edge of the source contacts. This decrease in mobility is due to the local peak in the electric field. Overall, the isothermal device has a high mobility along the channel, which corresponds to high current density in Fig. 5(a) as compared to the electrothermal simulation in Fig. 4(b).
Figure 6 provides a comparison of the electrothermal simulations to the equivalent isothermal simulations where the lattice temperature is fixed at 300 °K. The drain current at a drain voltage less than 3 V is similar in the thermal and isothermal simulations. This indicates that current density is sufficiently low such that the Joule heat generated can be effectively conducted to and dissipated at the base of the substrate. Additionally, although self-heating is minimal, it is clear the drain voltage is shifting the onset of saturation in drain current—for this particular device geometry and structure.
The drain current and transconductance at a drain voltage of 5 V show a small deviation in the thermal and isothermal simulations for a gate bias greater than −1 V. At this transition point, the current density is sufficiently high that most but not all the Joule heat generated can be effectively dissipated at the base of the substrate. For a drain voltage of 5 V, an inflection is present in the transconductance curve [Fig. 6(b)] at a gate bias of 1 V for both the thermal and isothermal simulation. This inflection corresponds to the point where the gate voltage is sufficiently positive such that the charge, located at modulation-doping position in the (Al0.25Ga0.75)2O3 barrier, is no longer depleted. For a drain voltage of 10 V, a similar inflection is present in the transconductance curve [Fig. 6(b)] at a gate bias of 2 V.
As discussed in Sec. II, at a drain voltage of 10 V, self-heating can raise the temperature of the lattice, which significantly decreases the electron mobility in and near the channel. This increases the resistance of the device, which is evident in the large difference in the thermal and isothermal simulations in Fig. 6.
Figure 6(a) shows a negative differential conductivity for a drain voltage above 7 V with a gate bias of −2 and 0 V. For this particular device structure, negative differential conductivity is not seen for the isothermal simulations. Here, two coupled mechanisms contribute to the negative differential conductivity; specifically, the sharp reduction in mobility at the drain side of the gate edge caused by the peak in the electric field, and the overall reduction in mobility along the entire length of the channel caused by the temperature rise related to self-heating.
C. Heat removal through the source metal
A simple improvement to the thermal design is to place a heatsink material on the surface of the structure near but offset from the source metal. Most transistor test structures have a large source pad above the source region; that is, the source contact is not accessed via a metal finger. As described above, the device surface is covered with an Si3N4 layer. A 50 nm Si3N4 layer is between the top of the source metal and the heatsink material, and the heatsink material is offset 5 μm from the edge of the source contact. To further simplify the analysis, no heat exits the bottom of the substrate.
Figure 7(a) shows that the drain current saturates at a drain bias greater than 7 V although a slight negative differential conductivity is evident at a drain bias of 10 V. Examination of the temperature cross section, in Fig. 7(b) reveals the expected peak at the drain side of the gate edge—and an overall gradient towards the heat sink located near the source contacts. The increase in temperature relative to the increase in power corresponds to a thermal resistance, Rth, of 114 mm K°/W at 10 V (and 327 °K). The thermal resistance (Fig. 7) for the source metal thermal contact is 41% the thermal resistance for the bottom substrate thermal contact (Fig. 3).
A similar thermal resistance of the overall device is found in a simulation (not shown) for a device formed on a 20 μm substrate with a bottom thermal contact. This result is reasonable as the 20 μm distance to the substrate base is similar to the distance from the drain edge of the gate to the source contact. Hence, thinning the substrate is another approach; however, the propensity for β-Ga2O3 to cleave discourages a postgrowth wafer thinning approach. Still, several works have demonstrated devices processed on exfoliated Ga2O3 films with a thickness typically less than 10 μm.10–13
A. Self-heating and mobility
Thermal management is an important design consideration in all semiconductor power devices.4,14 The simulations in this work show that self-heating owing to the low thermal conductivity of β-Ga2O3 dramatically lowers the mobility in the channel region, which increases the on-state resistance at moderate current densities. The low thermal conductivity of β-Ga2O3 necessitates advanced thermal management solutions for operation at even moderate power levels.15,16 Candidate solutions include flip-chip designs where heat is extracted globally from the top surface as well as more nuanced modification of the gate region to enhance local heat extraction at or near the gate.17–19 Naturally, thermal mapping of the device surface or depth directly measures the thermal response of the device.20 Nevertheless, these measurements can be obscured by the contact structure. Additionally, a thermoreflectance imaging measurement is complicated by the requirement for illumination greater than the wide bandgap of β-Ga2O3. As outlined in this paper, understanding the relation of self-heating on the response of the drain current to applied gate bias and drain voltage provides an additional assessment of the thermal management in the device structure.
B. Modulation doping considerations of β-Ga2O3 modulation-doped field effect transistor
The presence of residual charge at the point of modulation doping is undesired as this creates a secondary channel that hampers the ability to modulate the primary channel. This charge at the modulation-doping point can be confirmed by an inflection in the transconductance curve. Specifically, as this charge is spatially closer to the gate metal, this inflection occurs at a more positive gate bias relative to the primary channel, which is deeper in the structure.
See the supplementary material23 for design rules for the modulation-doped structure with a goal of maximizing the concentration of electrons in the potential well while minimizing the low-mobility secondary channel at the modulation-doped layer. An emphasis is placed on mitigating three limitations related to the deposition of β-Ga2O3, specifically, the inability to deposit high-quality β-(AlxGa1−x)2O3 with an aluminum mole fraction greater than approximately 0.25, the difficulty to deposit a high concentration of dopant atoms without the formation of its native oxide, and the unintentional dopant atom exponential decay tail. Simulations for an aluminum mole fraction of 0.25 show that proper selection of the barrier thickness and modulation-doping level, including accounting for any asymmetric broadening, can yield a dense electron channel confined primarily to the potential well at the (AlxGa1−x)2O3/Ga2O3 interface.
V. SUMMARY AND CONCLUSIONS
The wide bandgap and related high critical breakdown field of β-Ga2O3 enables a high-voltage lateral transistor designed for low on-resistance as well as operation at high frequency, which reduces the size and weight of the passive circuit elements in the overall system.21,22 In this work, an accurate approximation for mobility as a function of temperature and dopant concentration is presented and employed in an electrothermal simulation of an (AlxGa1−x)2O3/Ga2O3 modulation-doped field effect transistor (MODFET). A decrease in drain current was attributed to a position-dependent mobility reduction caused by a coupled self-heating mechanism and a high electric-field mobility reduction mechanism. Thermal management is a key design issue in all power semiconductor devices. The low thermal conductivity of Ga2O3 hampers any design where heat must flow over any appreciable thickness of Ga2O3. A heatsink via the source contact is discussed and shown to reduce the temperature of the active device channel.
The work at NRL was partially supported by DTRA under Grant No. HDTRA1-17-1-0011 (Jacob Calkins, monitor) and the Office of Naval Research. The work at UF was partially supported by HDTRA1-17-1-0011 and HDTRA1-20-2-0002. The content of the information does not necessarily reflect the position or the policy of the federal government, and no official endorsement should be inferred. The work at Korea University was supported by the Korea Institute of Energy Technology Evaluation and Planning (No. 20172010104830) and the National Research Foundation of Korea (No. 2020M3H4A3081799).
The data that support the findings of this study are available from the corresponding author upon reasonable request.