In this paper, the authors report the latest results on their development of superlattice-doped, thinned, backside-illuminated (BSI), 3D-integrated photodiode detectors—a step toward their ultimate goal of demonstrating ultrafast, ultrastable CMOS imaging arrays. As with most silicon-based photodetectors, backside-illumination and backside surface passivation are keys to achieve the highest performance capability. The two-dimensional (2D) doping technique developed at the Jet Propulsion Laboratory (JPL) has proved to result in a highly efficient, highly stable detector response when combined with a variety of detectors. Here, JPL's 2D-doping has been combined with Sandia's BSI photodetectors hybridized with custom fanout wafer via copper Direct Bond Interconnect (DBI®), a technology that is rapidly becoming industry standard for BSI CMOS imaging arrays. The prototype detectors were packaged and evaluated with respect to their response to low energy electrons. The authors find that the responsivity of 2D-doped BSI detectors is higher than devices prepared using other surface passivation techniques (i.e., ion implantation). The success of the work described herein verifies that the 2D-doping processes previously developed for Sandia's frontside-illuminated photodetectors are generally applicable to BSI detectors and demonstrates for the first time that JPL's 2D-doping process is compatible with the Cu-DBI® technology.

Silicon-based detectors and imaging arrays, especially charge-coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensors (CIS), are used in a variety of scientific and commercial applications. Since their invention in the late 1960s, silicon imaging arrays have benefited from a steady advancement of silicon very large scale integration technology and a booming consumer market. Their foray into space began with the 1989 launch of Galileo1 and has continued to the present day, where nearly every NASA mission includes a silicon imager.2–6 

CCDs have been the detector of choice for scientific applications in the visible and near infrared; however, with recent advances in low read noise capability, CIS have become contenders. CMOS image sensors are inherently more radiation tolerant than CCDs because their parallel readout (amplifier per pixel) design eliminates the cumulative effects of radiation-induced traps on charge transfer in CCDs. In addition, CMOS structure offers a selectable region of interest readout.

As with any system, the choice of detector depends on the intended use. Scientific-CMOSs are excellent candidates for space-based imaging and have been adopted in engineering cameras and context cameras for a variety of NASA missions including OCO-37 and Mars2020.8 CMOS image sensors were also flown on the Parker Solar Probe.9,10 CMOS image sensor development efforts at Sandia National Laboratories, some of which are described here, are partially focused on producing high performance, ultrafast x-ray imaging (UXI) detectors for fusion and high energy density physics. Sandia's Icarus and Icarus 2 sensors, developed for the UXI program, are burst-mode style imagers with nanosecond timing resolution.11–13 

Silicon's response to ionizing radiation—x-rays, ultraviolet light, energetic particles, and ions—has been extensively studied. CMOS detectors comprise arrays of p-i-n detectors, and the detection efficiency depends on the transport of photogenerated electron–hole pairs through the depletion region for collection. The electric field near the incident surface plays an important role in detection efficiency. In back-illuminated detectors, a high surface defect density can result in low detection efficiency for shallow-penetrating radiation. Within the so-called “dead layer”, photogenerated charge may be lost to recombination and never reach the depletion region. Thus, to improve (or enable) detection of shallow-penetrating radiation, near-surface defects must be passivated and the near-surface electric field tailored for high detection efficiency using the techniques of band structure engineering.

Conventional approaches to surface doping include using ion implantation and surface passivation using dielectrics grown or deposited to produce a highly doped surface with a low density of interface traps. In ion implantation, surface doping is achieved using an energetic ion beam to form a highly doped electrode in the near-surface region of the detector, followed by an annealing process to activate dopants and mitigate damage to the silicon lattice. The dopant is typically confined to within a few tenths of a micrometer of the surface; optimizing or narrowing the dopant distribution/density is achieved by using a shallower implant (i.e., lower energy beam), controlling the dose, and managing the thermal history. For surface passivation, high quality dielectric films (i.e., SiO2, Si3N4) are often deposited or grown on the detector surface in an attempt to control the surface defect density.

The approach to surface passivation at the Jet Propulsion Laboratory (JPL) is band structure engineering based on superlattice doping (2D-doping), a process in which a highly doped silicon layer is deposited on the photon-incident surface by molecular beam epitaxy (MBE). During MBE growth, an atomically thin, highly concentrated delta layer of dopants is embedded within nanometers of the surface.14 The MBE process allows for nanoscale control of dopant density and position within the deposited layer. Using this technique, dopant densities that exceed the solid solubility limit can be achieved with near 100% activation. JPL's 2D-doping has been demonstrated with a variety of silicon photodetector architectures, including photodiodes and avalanche photodiodes, CCDs, electron multiplying CCDs, CIS, and hybrid arrays (e.g., CMOS readout hybridized with silicon PIN diode arrays).15–24 

Photodetectors treated with JPL's 2D-doping process have proven to be extremely stable against surface damage. Quantum confinement effects within the 2D-doped layer result in exceptional stability for 2D-doped arrays and render the detector response insensitive to surface defect density.25–27 Hoenk et al. previously reported performance data from 2D-doped CMOS imaging arrays in which the detectors were subjected to lifetime tests under intense, long-term illumination by pulsed deep UV (DUV) lasers.22 Surface conductivity measurements performed on 2D-doped witness samples confirmed that exposure to the DUV lasers results in significant reduction in surface conductivity; however, the exposed 2D-doped CMOS imaging arrays remain stable to better than 1% quantum efficiency and dark current. Furthermore, the exposed devices exhibited high modulation transfer function and no measureable persistence even after >2 × 109 saturating pulses at 193 nm.

We previously reported on the effects of varying the surface preparation when producing detectors where temporal response and sensitivity are key elements. For this prior work, Sandia custom-fabricated frontside-illuminated (FSI) photodiodes with varied implant parameters, including implant type (p-type versus n-type), depth, and density; in some cases, the implant was omitted entirely. A subset of the fabricated wafers were then sent to JPL for 2D-doping. The 2D-doping parameters were also varied, including dopant type (p-type versus n-type), density, and the number of delta layers. Device performance was evaluated with respect to electron responsivity, visible light quantum efficiency, and pulsed x-ray response. From these studies, it was determined that detectors with a two-layer superlattice exhibited the highest responsivity while maintaining nanosecond timing response.28 

Here, we extend our studies to backside-illuminated (BSI) photodetectors hybridized with a custom fanout wafer as a step toward demonstrating ultrafast, BSI CMOS imaging arrays. The work described here also marks for the first time JPL's 2D-doping process has been applied to devices constructed using 3D stacking by direct bond interconnect (DBI®),29 demonstrating the compatibility of the two technologies.

The devices used for this study were designed and fabricated at Sandia's Microsystems and Engineering Sciences Applications facility. The major process steps are shown in Fig. 1.

The devices were made using a silicon-on-insulator material, where the 25 μm thick Si device layer is separated from the 675 μm thick Si substrate by an oxide buffer layer. The device layer comprises high purity (>3 kΩ cm) n-type silicon. The junction was formed by an ion-implanted p+ region, and the substrate contact was formed by an ion-implanted n+ region. The surface was covered with ∼2 μm of silicon dioxide with tungsten contacts to the ion-implanted regions and an embedded aluminum layer for signal routing. The completed photodiode wafers had an oxide surface with exposed tungsten vias.

A purpose-built fanout wafer was also designed and fabricated at Sandia National Laboratories to facilitate signal routing of the hybridized devices. These consisted of an aluminum metal routing layer embedded in silicon dioxide with exposed tungsten vias. These entirely passive devices were intended to route photodiode nodes out from under the photodiode layer to bond pads.

The photodiode wafers and fanout wafers were bonded using wafer-to-wafer DBI® technology.29,30 This process was performed using an external vendor. In this process, an oxide layer with interspersed copper features was added to both wafers. The wafers were then bonded together to create a bonded wafer stack with embedded electrical connections from the photodiode devices to the fanout routing layer. The photodiode wafer substrate was removed and the buried oxide layer was etched away, leaving the 25 μm thick device layer exposed with the illuminated device layer facing outward.

Following DBI, the hybridized wafers were sent to JPL for surface passivation by 2D-doping. The wafers were treated by standard clean (SC)-1 (5:1:3 water:hydrogen peroxide:ammonium hydroxide) and SC-2 (4:1:1 water:hydrogen peroxide:hydrochloric acid) each for 10 min. A rinse with de-ionized water followed both steps. Wafers were then exposed to a 30-min ozone treatment under ultraviolet illumination to remove any remaining hydrocarbons. Finally, wafers were transferred to nitrogen purged glove box for oxide removal by spin etch (1000 rpm) with (1) ethanol, (2) 5:1 ethanol:hydrofluoric acid solution, and (3) a final ethanol rinse; this process results in a hydrogen-terminated surface.31 The wafers were then loaded into the MBE without additional air exposure.

Details of the n-type 2D-doping process with antimony is described in detail elsewhere.32 Briefly, the wafers were processed in a Veeco Gen 200 MBE system with a base pressure of ∼5 × 10−10 Torr. Wafers were loaded onto silicon carbide platens and introduced to the system via load lock entry. Silicon was deposited by electron beam evaporation at a rate of ∼1 Å s−1 using a custom source (Island e-Beam). Antimony was evaporated from a valved cracker cell (Veeco; VCCS 100-420) with three zone heating control of the bulk, conditioning zone, and cracker tip temperatures; for this work, the set points were 400, 850, and 1100 °C, respectively. The superlattice structure comprised a 2.5 nm silicon buffer layer, two antimony delta layers separated by a 1 nm silicon spacer, and a 2.5 nm silicon cap layer. The buffer layer was deposited at a substrate temperature (Ts) of 425 °C, then the sample was cooled and the rest of the structure was deposited at Ts= 350 °C. Dopant density within each delta layer was ∼2 × 1014 cm−2.

The devices were completed by adding a backside electrode and opening bond pads at Sandia. A metal grid electrode was added to the illuminated surface by a multistep process intended to protect the thin superlattice structure. A blanket 10 nm Ti coating was deposited on the detector surface, followed by a lift-off pattern of 500 nm Al. The exposed Ti was removed by hydrogen peroxide or TBR-19 etchant. The detector device area was defined by Si dry etch removal of the device layer outside the active area. Finally, a dielectric dry etch was used to reveal the bond pads. Devices were separated by dicing and packaged in a bulkhead adapter in a similar fashion to the scheme described in Looker et al.28Figure 2 shows a photograph of a packaged device.

Electron responsivity measurements were used to evaluate device performance. This is a sensitive test of device surface conditions because the electrons deposit the majority of their energy within a few hundred nanometers of the surface. The details of the method for measuring e-responsivity has previously been described in detail.28 Briefly, a scanning electron microscope (SEM) was used as the electron source, with a nominal beam current of 100 pA and an electron energy (Ee) range from 0.5 to 10 keV. At each Ee step, the beam current was measured with a Faraday cup and the detector current was measured using a source-measurement unit.

Electron responsivity data are shown in Fig. 3. The data show that 2D-doped, BSI 3D-stacked Sandia detectors perform near the theoretical limit, with significant response observed even at the lowest energy studied. This finding agrees well with those previously observed for 2D-doped FSI Sandia detectors.28 Conversely, the performance of ion-implanted devices falls short of the theoretical limit, with a marked drop in responsivity for the lower end of the Ee range studied. Passivating the surface of ion-implanted devices with deposited SiO2 results in only a slight improvement in performance, while passivating with Si3N4 further improves response for Ee ≥ 2 keV.

The relative low responsivity of the ion-implanted BSI devices suggests that charge is being lost to recombination both at and near the surface. The absorption depth of electrons in silicon follows a near-linear relationship with respect to Ee. For incident electrons having energies within the range studied here (0.5–10 keV), all are absorbed within 1 μm of the back surface; this number is reduced to <0.1 μm as Ee approaches 1 keV.33 Typical ion implantation depths are on the order of several tenths of a micrometer, thus providing sufficient space/time for recombination and limiting response within our Ee range of interest. Prior work at Sandia showed that using a shallower implant resulted in a moderate improvement in the responsivity of FSI devices, attributable to a decrease in the dead layer thickness.28 

As previously indicated, surface passivation by depositing high-quality films (e.g., oxides, nitrides) has long been used as a method of reducing the density of trapping states at the surface. Silicon's native oxide typically forms with a high density of defects at the surface interface, resulting in a fixed net positive charge and surface depletion.34,35 Passivating films must provide a stable, negative charge with a charge density high enough to create a near-surface electric field sufficient to exclude minority carriers, thus suppressing surface recombination.34–37 This phenomenon is illustrated with the ion-implanted BSI devices with SiO2 and Si3N4 coatings; the improved response of these devices can be attributed to a reduction in surface recombination; however, the overall performance remains limited by bulk recombination. It is also important to note that passivating films are themselves susceptible to environmental effects, such as radiation-induced damage, that can result in charging within the film, resulting in time variable response or a permanent reduction in performance.38–41 

JPL's 2D-doping is significantly different from the other passivation techniques typically used. Standard 3D-doping techniques, such as ion implantation, often result in poor crystalline quality and low minority carrier lifetimes in the near-surface (i.e., implantation) region, often to a depth of several hundred nanometers. Additionally, dopant atoms are often only partially activated due to clustering and incorporation into interstitial sites. Conversely, our team at JPL has previously demonstrated that with 2D layers, it is possible to produce films with total thickness less than 5 nm and dopant densities more than an order of magnitude higher than the solid solubility limit that constrains 3D doping methods. It has also been reported that 2D-doping can result in dopant density levels on the order of 1019–1020 cm−3 with near unity activation.32,42–45 2D-doping by MBE incorporates dopant atoms in a highly uniform, self-organized 2D layer. The process is marked by high crystalline quality and a surface phase stabilized by covalent bonds with the silicon lattice. The extreme high doping levels in the 2D-doped surface passivation layer essentially eliminate the dead layer. Thus, the low response attributed to bulk recombination in ion-implanted devices is eliminated, and 2D-doped devices exhibit higher response throughout the entire Ee range studied. Furthermore, quantum confinement effects within the superlattice greatly reduce the residence time of minority carriers near the interface, effectively suppressing surface recombination. Therefore, the 2D-doping approach to surface passivation obviates the need for other backside charging techniques.22 

DBI® hybridization technology is rapidly becoming industry standard for 3D-stacked CIS. The DBI® approach has the advantage of allowing optimization of detector and readout architecture independently. The 3D stacked hybrid approach allows for small pixels and also overcomes the limits of conventional CIS for tiling in mosaic focal plane arrays by moving the extra circuitry from the array periphery to a vertically integrated structure.46,47 DBI® is a low temperature process that is fully compatible with multilevel back-end-of-line CMOS interconnects.29,48 The technique involves aligning and placing two surfaces into contact; often, a postbond anneal is used to facilitate 3D electrical interconnections.48 When employing a Cu-DBI® process, as was done in this work, a postbond anneal of 150–300 °C is typically used. This temperature is significantly lower than the 425 °C required for the 2D-doping process, raising concerns regarding the compatibility of the two processes.

Figure 4 shows a scanning electron microscopy (SEM) cross section of the 3D-integrated device following 2D-doping. Note that the copper interconnects and through-silicon vias show no signs of degradation or void formation even after exposure to the high temperature (425 °C) required for the 2D-doping process. These results demonstrate for the first time that JPL's 2D-doping is compatible as a passivation step for 3D-stacked CIS hybridized via copper DBI®.

Here, we have reported on the development and characterization of 2D-doped, BSI, 3D-integrated photodetectors. The 2D-doped detectors outperform ion-implanted BSI devices, both with and without additional surface passivation, in electron responsivity tests. The work done here demonstrates that processes previously developed for n-type 2D-doping of FSI photodetectors are compatible with the 3D-stacked CMOS image sensor. This joint venture between JPL and Sandia represents a major step forward in demonstrating ultrastable, ultrafast CMOS imaging arrays. Combining DBI® hybridized ultrafast CMOS sensors—such as Sandia's Icarus detector—with JPL's 2D-doping creates a powerful technological approach for meeting all of the detector requirements set forth for Sandia's UXI program as well as NASA's future flagship missions.

The research described in this paper was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration, and at Sandia National Laboratories. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under Contract No. DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

April D. Jewell is a member of the Technical Staff in the Advanced Detectors, Systems and Nanoscience Group at the Jet Propulsion Laboratory (JPL). She has degrees from George Washington University (BS, Chemistry) and Tufts University (PhD, Chemistry). Her current work is focused on optimizing silicon-based imagers for project- or mission-specific applications through postfabrication, surface-level processing.

Dr. Jewell's graduate research explored fundamental surface-level chemical interactions by capturing and manipulating molecular events occurring at the gas–solid interface. Her graduate work aimed at understanding and exploiting surface-scale phenomena with respect to reactivity and self-assembly has been key to her current work at JPL, which is a combination of material science and process development. Dr. Jewell uses two main processes to control the surface-level properties of detectors: molecular beam epitaxy (MBE) for surface band structure engineering and atomic layer deposition (ALD) for nanometer-scale coatings and filters. Dr. Jewell's background in surface science allows her to develop MBE and ALD processes that are general enough to be applied to virtually any silicon-based imager.

Dr. Jewell has received multiple awards and honors for her work in both graduate school and at JPL. Based on her graduate research, Dr. Jewell was awarded the Russell and Sigurd Varian Graduate Student Award from the American Vacuum Society (AVS) and the Morton M. Traum Student Presentation Award from the AVS Surface Science Division, as well as the Young Scientist Prize at the 10th International Conference on the Structure of Surfaces. Dr. Jewell was recently honored as a 2019 Rising Researcher by the International Society for Optics and Photonics (SPIE) and as a recipient of JPL's Charles Elachi Award for Early Career Achievement. In addition, she has received a NASA Honor award, JPL's Voyager and Discovery Awards, and a Guinness world record for the smallest electric motor.

Dr. Jewell has coauthored over 60 manuscripts and three book chapters and is a coinventor on multiple U.S. patents. She has contributed over two dozen conference presentations, including four invited presentations, and has sat on conference panel discussions.

Throughout her career, Dr. Jewell has engaged in outreach activities—mentoring local high school students, volunteering for JPL-wide community activities, visiting inner city schools for in class demonstrations, and making YouTube videos describing her team's research. April is a proud volunteer with Los Angeles Animal Services and is the de facto captain of her bowling team and pub trivia group.

A note from the author to her 16-year-old self: Ask questions!

Throughout college and early in my career, I avoided asking questions. I was worried about coming across as uninformed (at best) or unintelligent (at worst), only to learn later that my classmates or colleagues had the same questions.

By choosing a career in the sciences, we have proven ourselves curious. But far too often, particularly in face-to-face situations or at the end of someone's presentation, we leave the question—our question—unasked. By doing so, we are missing out on critical learning opportunities, not just for ourselves, but for our colleagues as well.

It took me years to realize that it is okay to be uninformed, and that choosing silence over potential embarrassment does nothing to help my education. I have come to appreciate that the person in front of me (or at the front of the room) is often the best expert on the very topic I have questions about, and they are there to answer (and learn from!!) my questions.

So if I could give only one piece of career advice to my 16-year-old self it would be to ask questions. Ask questions of your teachers, your classmates, your colleagues, the seminar speaker, the person giving the conference presentation, and the people you may one day work for, with, or above. Simple in theory, but occasionally daunting in practice, asking questions is vitally important … and its the best way to learn.

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