Ultrathin Stable Ohmic Contacts for High-Temperature Operation of $\beta$-Ga$_2$O$_3$ Devices

Beta gallium oxide ($\beta$-Ga$_2$O$_3$) shows significant promise in the high-temperature, high-power, and sensing electronics applications. However, long-term stable metallization layers for Ohmic contacts at high temperature present unique thermodynamic challenges. The current most common Ohmic contact design based on 20 nm of Ti has been repeatedly demonstrated to fail at even moderately elevated temperatures (300-400$^{\circ}$C) due to a combination of non-stoichiometric Ti/Ga$_2$O$_3$ interfacial reactions and kinetically favored Ti diffusion processes. Here we demonstrate stable Ohmic contacts for Ga$_2$O$_3$ devices operating up to 500-600$^{\circ}$C using ultrathin Ti layers with a self-limiting interfacial reaction. The ultrathin Ti layer in the 5nm Ti / 100nm Au contact stack is designed to fully oxidize while forming an Ohmic contact, thereby limiting both thermodynamic and kinetic instability. This novel contact design strategy results in an epitaxial conductive anatase titanium oxide interface layer that enables low-resistance Ohmic contacts that are stable both under long-term continuous operation (>500 hours) at 600$^{\circ}$C in vacuum ($\leq$ 10$^{-4}$ Torr), as well as after repeated thermal cycling (15 times) between room temperature and 550$^{\circ}$C in flowing N$_2$. This stable Ohmic contact design will accelerate the development of high-temperature devices by enabling research focus to shift towards rectifying contacts and other interfacial layers.


I. INTRODUCTION
β-Ga2O3 is a strong candidate for next-generation high-temperature electronic device manufacturing for both power and sensing applications. As a material it shows excellent figures of merit for high-voltage operation and high frequency switching, due to its large bandgap and high theoretical breakdown field [1][2][3] . Additionally, β-Ga2O3 is readily n-type dopable at shallow levels, with Si and Sn being the most common dopants 1 . From a manufacturing perspective, single-crystal Ga2O3 substrates can be grown by both Czochralski (CZ) and edge-defined film-fed growth (EFG), which allows for potential industrial scaling. Projective cost modeling suggests that as the technology develops, the economic viability and technological value of Ga2O3-based devices will continue to improve and be competitive with existing SiC and GaN technologies 4,5 .
Reliable and stable Ohmic contacts are enabling for all types of Ga2O3-based devices. Currently, many groups use some variation of the commonplace Ti/Au metallization scheme, where most frequently a Ti layer of at least 20nm is applied, followed by a chemically protective and electrically conductive Au layer [6][7][8][9][10][11][12][13][14][15][16][17][18] . Variations that include additional diffusion barrier layers are also common [19][20][21][22][23][24] . This contact scheme is most frequently annealed at 470 ℃ for 90 seconds in nitrogen. Titanium is chosen as an interlayer due to its good adhesion to both semiconductors/oxides and to other metals, as well as its desirable electrical properties -Ohmic contacts of this design regularly demonstrate minimal degradation at or around room temperature operation. For Ga2O3-based devices, this contact scheme has demonstrated low specific contact resistances, on the order of 10 !" Ω cm # for traditional n-type substrates 16,17 , and between 10 !$ − 10 !% Ω cm # for surface treated substrates (e.g., ion implantation) 12,13 .
While these contacts demonstrate acceptable stability at room temperature, few studies have examined the effects of long-term, high-temperature operation on their performance; to date, the few studies done reveal significant problems with rapid contact degradation even at relatively modest temperatures (300-400 ℃). One group showed that a Si-implanted substrate treated with a reactive ion etch demonstrated stability with this metallization scheme over the course a 100+ hours thermal aging procedure at 300℃.
Compared to this treated substrate, the contact resistance of an untreated metalsemiconductor junction increased by almost 40% over the same period 17 . Another group subjected a vertical Schottky device with a 20nm Ti / 100nm Au Ohmic contact to repeated thermal cycling, up to 410℃, and found that the series resistance of the device increased by several orders of magnitude 18 . This is problematic for applications where operation to 600℃ is desired.
Degradation of this standard Ohmic contact design is hypothesized to be due, at least in part, to the formation of a 3-5 nm Ti/TiOx "defective" interfacial layer between the Ga2O3 and the Ti contact. This is supported by thermodynamic analysis, as annealing can provide conditions that are favorable for the formation of several different titanium oxides, resulting in redox reactions between the titanium and gallium oxide. This is thought to result in a gallium-rich sub-oxide layer in contact with a TiOx sub-oxide layer.
Problematically, the remainder of the unreacted Ti either forms nanocrystals within the Au 16 or migrates through the Au to the outer surface over time, likely due to favorable thermodynamic driving factors (i.e., gradients in oxygen chemical potential), as well as facile Ti-diffusion kinetics that increase with temperature 18,25 . As such, electrical performance can be marred by the high Ti mobility and its redistribution during device operation. Both the formation of an oxide layer on top of the gold contact layer, as well as the formation of nanocrystalline scattering sites, are thought to reduce the performance and reliability of the Ohmic contact.
While Ti migration is thought to be detrimental to contact stability, the thin Ti/TiOx "defective" interfacial layer that forms between the Ga2O3 and the Ti contact can potentially be beneficial. Several studies of the oxidation state of Ti at the Ti/Ga2O3 interface suggest the presence of various TixO(2x-1) Magnéli phases, which have been shown to be highly conductive and stable in oxidizing environments [26][27][28][29] . These findings suggest that leveraging and controlling the interfacial reaction while minimizing excess mobile Ti can potentially be used to improve contact stability.
In this report, we show that an ultra-thin titanium interlayer maximizes the completion of the reaction with the Ga2O3 substrate while minimizing subsequent Ti diffusion. We first compare the performance of a Ti/Au contact to (001) Sn:Ga2O3 with 5nm and 10nm of titanium through repeated thermal cycling (15 times) in a N2 atmosphere. We find that the 10nm thick Ti contact shows both greater series resistance and inconsistent thermal and temporal behavior. In contrast, the 5nm thick Ti contact shows excellent stability and performance under long term temperature cycling. We then further validate the 5nm thick Ti contact design by fabricating a series of 12 double-Ohmic vertical devices which we subject to extended high-temperature thermal treatment (600℃) in a vacuum chamber (≤ 10 !& Torr) for >500 hours. We find that all 12 devices show excellent performance, stability, and repeatability during this extended hightemperature exposure. Through TEM analysis of the thermally cycled samples, we find that high-temperature operation of the 5nm samples results in the formation of a highly crystalline, epitaxial titanium oxide interfacial layer which we hypothesize contributes to the reliable, conductive Ohmic contact behavior. Conversely, TEM investigation reveals incomplete oxidation of the thicker 10nm Ti-based contacts, which corelates with the unstable thermal and temporal behavior of these devices. This also likely explains the thermal instability of the even thicker 20nm Ti-based contact scheme commonly adopted in the field. We find that diffusion of Ti to the outer surface occurs in both 5nm and 10nm Ti samples, suggesting that its effects are secondary to those of the interfacial contact layer quality.

A. Sample Preparation
Devices were fabricated using (001) Sn-doped Ga2O3 from Novel Crystal Technologies. Photoresist was removed from the as-delivered substrate via an organic wash, followed by a sulfuric acid/peroxide rinse. The bi-metal deposition of Ti/Au via ebeam was performed with a Temescal FC2000 Evaporation System in high-vacuum (≤

B. Electrical Characterization
For thermal cycling, two-probe measurements (source I, measure V) were performed by a Keithley 236 SMU in an Instec HCP621G-PMH probe station under flowing nitrogen at 40 sccm. A single thermal cycle consisted of ramping from 25℃ to 550℃ and back down to 25℃ in 75℃ increments. Each temperature increment was allowed to equilibrate for 15 minutes before electrical measurements were performed.   Significant variability in the measured series resistance was observed for the 10nm sample, especially with increasing cycle number. The first 8 cycles produced relatively consistent resistance values that gradually increased from ≈ 0.6 Ω cm # (cycle 1) to ≈ 1.4 Ω cm # (cycle 8). Series resistance was highest at room temperature and trended towards a minimum at 325℃ before gradually increasing again at still higher temperatures. After the first 8 cycles, the series resistance behavior became less consistent, particularly at lower temperatures, with values ranging between ≈ 1.5 − 5 Ω cm # , representing an increase of 250-900% compared to the initial cycle behavior.

A. Thermal Cycling
In contrast, the 5nm sample exhibited extremely stable and consistent behavior.

B. Thermal Soaking
After reaching 600℃, the series resistance of the 12 devices were periodically measured every 1-3 days. An alumina platform with the same metallization scheme (5nm Ti / 100nm Au) was utilized to access the back Ohmic contact of the device. Shown in Figure 3, the average series resistance of the 12-devices decreased in magnitude from an initial value of 7.7 ± 2.09 Ω to a final value of 5.95 ± 0.23 Ω over the course of the >500-hour thermal soak at 600℃. Note that these values are reported in Ω instead of Ω cm !# as they include the probe tip resistance, leads, etc., which were found to contribute significantly to the overall resistance. Measurements of each of these contributions were attempted; however, they yielded results that proved too difficult to deconvolve. Hence, we report the lumped resistance values in their entirety. See supplementary material at [URL will be inserted by AIP Publishing] for full results of both TLM measurements and back platform resistances. The first ≈ 50 hours of thermal soaking produce the greatest variability; after this, all variations seen in the average series resistance across all devices are within one standard deviation of the mean. This behavior suggests a 'break-in' period occurs during the initial ~50hr period at temperature during which thermal or electrical processes drive the system towards a stable equilibrium.

C. TEM/EDS Analysis
To understand this behavior, TEM lamellae were prepared from cycled samples of both the 5nm and 10nm Ti layer contacts using an FEI Helios Nanolab 600i, following standard lift-out techniques and using a 2kV clean final step to minimize sample damage 31 . The 5nm specimen was capped with carbon via permanent marker before FIB lift out to protect the top surface, while the 10nm specimen was capped only with electron-beam Pt GIS deposit followed by ion-beam Pt GIS deposit. The 5nm specimen was lifted out parallel to the substrate (010) plane while the 10nm specimen was lifted out parallel to (100). The TEM specimens were analyzed in an FEI Talos   indicate that this outer Ti layer is oxidized. Since sample preparation was carried out using a Ga FIB, contamination giving the impression of Ga presence cannot be discounted. However, the 5nm Ti specimen provides good evidence that this Ga layer is real and not an artifact since the carbon capping contains no Ga and is sufficiently thick to protect the buried Au surface from any Ga implantation due to the milling process. Ga implantation from the side during sample thinning would be expected to be consistently dense throughout and mostly removed by the final 2kV polish.
The bottom two panels of Figure 4 show HAADF images of the 5nm and 10nm samples, contrasted by atomic number. The Ti contact appears as the thin dark layer in both TEM images. In both cases, the actual Ti layer thickness observed in the TEM cross sections is slightly smaller than nominal target thickness (~8nm for "10nm" contact and 4.5-4.7nm for "5nm" contact), demonstrating the need for a high degree of precision when fabricating contacts. Additionally, the Ti layer of the 10nm specimen shows slightly more thickness variation. The single-crystal Ga2O3 substrate underlying the 10nm Ti sample (bottom layer in the TEM image) has vertical striations most likely due to more aggressive specimen preparation curtaining the lamella or possibly due to differences in milling behavior of the differing crystallographic plane of the substrate.   The grains are not epitaxial and only some diffraction patterns are on a discernable zone.
Both rutile and brookite diffraction patterns are identifiable, but with significant amorphous character. However, this amorphous contribution could come largely from the protective capping added during sample preparation rather than the sample itself.
Although not investigated, we presume that the TiOx clusters formed on the top Au surface of the 10nm sample are similarly structured with a mix of rutile, brookite, and amorphous TiOx.  To summarize, TEM analysis shows that in both the 5nm and 10nm cases, the Ti layer forms epitaxial anatase phase TiO2; Ti migrates to the surface and forms unevenly distributed titanium oxide patches; and Ga also migrates to both the Ti-Au interface and the surface and forms a thin, evenly distributed layer. The key difference between the two specimens is that the 5nm anatase layer is fully crystalline whereas the 10nm anatase layer contains a substantial amount of amorphous TiOx second phase that affects the performance of the Ohmic contact.

IV. SUMMARY AND CONCLUSIONS
We have successfully fabricated Ohmic contacts to Sn:Ga2O3 using an ultra-thin layer of Ti (5nm) with a Au capping layer (100nm). These contacts show remarkable stability and excellent Ohmic performance after both extensive thermal cycling between 25 -550℃ in N # and long-term thermal soaking at 600℃ for ≥ 500 hours under vacuum conditions. Through TEM analysis, we show that the 5nm Ti layer is sufficiently thin that it completely transforms to an epitaxial, highly conductive anatase titanium oxide layer which provides a stable Ohmic contact. In contrast the 10nm Ti layer does not fully react, leading to a partially amorphous TiOx layer that does not enable a stable Ohmic contact.
While Ti is found on the outer surface of the Au layer in both 5nm and 10nm Ti samples, the homogeneity of the interlayer at the Ga2O3 interface appears to have a greater impact in the overall performance and stability of the contact. Integration of this ultrathin Ohmic contact design will aid development of high-temperature devices, by specifically shifting research focus to stable Schottky metals, p-type heterojunction materials, and other functional layers.

Conflicts of Interest
The authors have no conflicts to disclose

Author Contributions
Ohmic contact design and testing:

DATA AVAILABILITY
The data that supports the findings of this study are available within the article [and its supplementary material].