The processing options available to fabricate multilevel metal interconnects are becoming greatly reduced as circuit dimensions enter the submicron regime. Advanced lithography techniques are required, such as x ray, electron‐beam, or monochromatic steppers. The choice of metal materials is small, due to resistivity and interconnect dimension requirements. Sputter deposition equipment has difficulty in depositing the metal into the high aspect ratio vias and new processes with superior stepcoverage are required. Other processing technologies are also experiencing difficulties as dimensions shrink. This paper discusses the utilization of certain advanced processing technologies, namely: stepper lithography, TiW capped AlCu metallization, chemical vapor deposition (CVD) tungsten, plasma deposited oxide (tetraethylorthosilicate source), and etchback planarization to successfully fabricate a submicron two‐layer metal structure. The test vehicle had via chains increasing in length from 10–8000 vias with dimensions from 0.75–1.5 μm. Serpentine metal patterns ranged from 0.001–1.1 m in length with pitch of 1.75–3.0 μm. Fabrication issues and potential solutions, as well as electrical data obtained from the test vehicle are presented. The electrical data includes metal serpentine yield and via chain data, comparing: (1) warm deposited AlCu, (2) hot deposited AlCu, and (3) CVD tungsten filled vias.

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