Electrical measurements were made on silicon on sapphire (SOS) before processing to the device stage. The objective was to determine process conditions for producing high‐resistivity, high‐mobility SOS. The phenomenological approach was used to study variations in electrical properties across a wafer. Conductivity‐type measurements were made where large variations in the resistivity occurred. A p‐type autodoping pattern was observed and traced to aluminum diffusion into the episilicon layer from sapphire substrate defect areas which were identified by scanning electron microscopy. Process parameters were adjusted to eliminate patterned autodoping. The average of point‐to‐point resistivity parameter values was then equal to the value determined for the whole wafer using peripheral contacts. The resistivity parameter was influenced both by carrier concentration and microstructure. The Hall mobility was highest for material where patterned autodoping was absent. If the silicon deposition temperature was lowered too much, the Hall mobility decreased significantly. Resistivity parameter mapping and mobility measurements were necessary to fix epigrowth parameters.

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