Tungsten diselenide, WSe2, is attractive as a channel material for p-channel metal–oxide–semiconductor field effect transistors (PMOSFETs) using transition metal dichalcogenide (TMD) nanosheets for ultimate CMOS scaling. For practical applications, it is necessary to demonstrate good quality devices on as-grown, large-area chemical vapor deposition (CVD) grown TMD films, rather than on small, exfoliated flakes from bulk crystals, and without requiring transfers to secondary substrates. This article reports on the growth optimization of large-area WSe2 and efforts to achieve higher hole conduction, which is more challenging than electron conduction since most TMDs tend to be n-type due to defects. Achieving low contact resistance and high drive currents is vital, but the intrinsic defects within the grown material dominate the carrier mobilities and effectively make TMDs more n-type due to chalcogen vacancies in devices fabricated at high temperatures. We have, therefore, developed salt-assisted growth strategies at different growth temperatures using atmospheric pressure CVD (APCVD). Furthermore, we identified optimal APCVD growth and PMOSFET fabrication recipes to achieve high hole conduction. With growth and fabrication optimization, we can achieve drive currents of 10 μA/μm in back-gated PMOSFETs at Vd = −2 V in as-grown WSe2, akin to their exfoliation-based counterparts. We also have seen evidence of both hole and electron ambipolar conduction even with high work function source/drain contact metals, signifying that contact engineering will be vital to suppress the electron branch and improve hole conduction.
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Enhancing chemical vapor deposition growth and fabrication techniques to maximize hole conduction in tungsten diselenide for monolithic CMOS integration
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March 2025
Research Article|
February 13 2025
Enhancing chemical vapor deposition growth and fabrication techniques to maximize hole conduction in tungsten diselenide for monolithic CMOS integration
Jatin Vikram Singh
;
Jatin Vikram Singh
(Conceptualization, Data curation, Methodology, Visualization, Writing – original draft, Writing – review & editing)
1
Microelectronics Research Center, Chandra Department of Electrical and Computer Engineering, University of Texas at Austin
, Austin, Texas 78758
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Matthew N. Disiena
;
Matthew N. Disiena
(Methodology, Writing – review & editing)
1
Microelectronics Research Center, Chandra Department of Electrical and Computer Engineering, University of Texas at Austin
, Austin, Texas 78758
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S. S. Teja Nibhanupudi
;
S. S. Teja Nibhanupudi
(Formal analysis, Methodology)
1
Microelectronics Research Center, Chandra Department of Electrical and Computer Engineering, University of Texas at Austin
, Austin, Texas 78758
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Nicholas T. Watanabe
;
Nicholas T. Watanabe
(Methodology)
1
Microelectronics Research Center, Chandra Department of Electrical and Computer Engineering, University of Texas at Austin
, Austin, Texas 78758
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JaeHyun Ahn
;
JaeHyun Ahn
(Methodology, Resources, Writing – review & editing)
2
Semiconductor R&D Center, Samsung Electronics Co. Ltd.
, Hwaseong, Gyeonggi 18448, Korea
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Dong-Won Kim;
Dong-Won Kim
(Methodology, Resources, Writing – review & editing)
2
Semiconductor R&D Center, Samsung Electronics Co. Ltd.
, Hwaseong, Gyeonggi 18448, Korea
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Anupam Roy
;
Anupam Roy
(Conceptualization, Data curation, Investigation, Supervision, Validation, Writing – original draft, Writing – review & editing)
3
Department of Physics, Birla Institute of Technology Mesra
, Mesra, Ranchi, Jharkhand 835215, India
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Sanjay K. Banerjee
Sanjay K. Banerjee
(Formal analysis, Funding acquisition, Methodology, Project administration, Resources, Supervision, Writing – review & editing)
1
Microelectronics Research Center, Chandra Department of Electrical and Computer Engineering, University of Texas at Austin
, Austin, Texas 78758
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J. Vac. Sci. Technol. A 43, 022201 (2025)
Article history
Received:
July 10 2024
Accepted:
January 15 2025
Citation
Jatin Vikram Singh, Matthew N. Disiena, S. S. Teja Nibhanupudi, Nicholas T. Watanabe, JaeHyun Ahn, Dong-Won Kim, Anupam Roy, Sanjay K. Banerjee; Enhancing chemical vapor deposition growth and fabrication techniques to maximize hole conduction in tungsten diselenide for monolithic CMOS integration. J. Vac. Sci. Technol. A 1 March 2025; 43 (2): 022201. https://doi.org/10.1116/6.0003893
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