Hf_1−xZr_xO₂ and HfO₂/ZrO₂ gate dielectrics with extremely low density of interfacial defects using low temperature atomic layer deposition on GaN and InP

Achieving a negative capacitance field effect transistor with a subthreshold swing beyond the Boltzmann limit requires a “defect-free” dielectric-semiconductor interface. We grew alloyed (Hf_1−xZr_xO₂) and stacked (HfO₂/ZrO₂) gate dielectrics on GaN and InP substrates using low temperature plasma enhanced atomic layer deposition. In situ ellipsometry data show that alloying hafnia with zirconia reduces the refractive index and widens the bandgap. The stacked and alloyed structures reveal very low capacitance-voltage hysteresis of 35 and 45 mV, respectively, on GaN. The density of interfacial traps as low as 1.12 × 10¹⁰ cm⁻² eV⁻¹ was achieved on GaN mainly due to the combination of very low dielectric growth temperature (100 °C) and high postfabrication heat treatment temperature (510 °C). The conduction and valence band offsets of the alloyed gate dielectrics on InP were measured and compared to pure zirconia using a combination of x-ray photoelectron spectroscopy and ellipsometry. The alloyed structures show a wider bandgap, larger conduction band offset, and smaller valence band offset compared to pure zirconia. This was attributed to the increase in the valence band width with hafnia addition, which reduces the alloyed gate dielectric’s valence band offset. We resolved the band structure alignement to be type I with band offsets of 3.53 eV for electrons and 1.03 eV for holes in Hf_0.25Zr_0.75O₂/InP heterojunctions. The results allow for a clear and detailed picture of two distinct growth procedure that affect the interfacial defect concentration.