Gate patterning strategies to reduce the gate shifting phenomenon for 14 nm fully depleted silicon-on-insulator technology

The complexification of integrated circuit designs along with downscaling introduces new patterning challenges. In logic process integration, it is found that the gate etch process flow introduces a few nanometer displacement of the gate patterns from their original position fixed by the lithography layout. This phenomenon referred to gate shifting (GS) generates a contact to gate overlay misplacement that compromises the transistor electrical performance. HBr cure plasma, which is a well-established postlithography treatment to increase photoresist stability and improves both line edge roughness (LER) and critical dimension uniformity during pattern transfer, has been identified as the root cause of the gate shifting phenomenon. The vacuum ultraviolet (VUV) irradiation emitted by HBr plasma leads to an asymmetric flowing of the two-dimensional resist patterns, and thus to a displacement of the gate patterns. Based on plasma optical emission measurements, the HBr plasma conditions are optimized to limit the VUV irradiation. If the GS phenomenon can indeed be eliminated using low VUV dose HBr plasma conditions, it introduces some strong LER issue during the subsequent Si antireflective coating (Si ARC) fluorocarboned plasma process. Indeed, low VUV dose HBr cure plasma does not play anymore its hardening role. The elimination of the GS issue is a priority for the transistor electrical performance. The strategy adopted in this study is to remove the HBr cure treatment and to optimize the subsequent Si ARC etch plasma process to minimize LER degradation during this step. The developed SF₆/CH₂F₂ Si ARC plasma etching process uses low energy ion bombardment combined with a fluorine rich chemistry to avoid the formation of a fluorocarbon polymer on the resist pattern, which is the main contributor for resist surface and sidewalls roughening. The new gate patterning process flow that is proposed in this article allows to eliminate the GS phenomenon but also to improve the final gate LER from 3.5 to 2.8 nm. Moreover, the study highlights the capability of the developed SF₆/CH₂F₂ Si ARC plasma chemistry to address the most advanced nodes with even more aggressive gate dimensions by eliminating the wiggling phenomenon occurring with previous Si ARC plasma chemistries for gate dimension inferior to 25 nm.