Dry etching is used for a number of processing steps in the fabrication of small geometry (∼2×5 μm2 emitter dimension), high speed (fT, fmax≥50 GHz) heterojunction bipolar transistors, including emitter, base, and collector mesa definition, sidewall etch‐back, and trilevel resist patterning. These steps involve the use of numerous plasma chemistries (CCl2F2 or BCl3 for GaAs/AlGaAs, CH4/H2 for InGaAs/InP, SF6 for dielectric sidewalls, and O2 for resist). We have conducted a systematic study of the threshold dc self‐biases for these discharges below which there is no significant damage introduction in the semiconductor. In a low pressure hybrid electron cyclotron resonance‐radio frequency reactor, these biases are a function of the doping type, doping level and the thickness of the exposed III–V layers. Changes in the sheet resistance and diode ideality factor of pn junctions in each material system were examined as a function of the time (1–20 min), plasma pressure (1–20 mTorr), and additional rf‐induced dc bias to obtain the optimum dry etch conditions. In our structures, dc biases of ≤−100 V appear to yield damage free etching. At higher biases, the damage depth dependence on bias was examined using the Seaward and Moll [J. Vac. Sci. Technol. B 9, 1445 (1991)] model and also by direct CV profiling.  

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