Twenty-four-micrometer-pitch microelectrode array with 6912-channel readout at 12 kHz via highly scalable implementation for high-spatial-resolution mapping of action potentials Open Access

High-resolution imaging of action potentials (APs) in cells can reveal the answers to questions regarding the complexities of neuron network activities, such as the nature of dendritic integration, the electrical functions of dendritic spines, and variations in spontaneous native activity patterns or network oscillations.^1,2 Action potentials have been widely studied through the use of patch clamps or fluorescence imaging methods.^3,4 While the patch clamp method can measure the action potentials directly and with high temporal resolution, the fluorescence method can provide two-dimensional (2D) high-spatial resolution imaging of the action potentials.

In the previous decade, a microelectrode array (MEA) with readout circuit integration via complementary metal-oxide-semiconductor (CMOS) technology was introduced to achieve 2D high-spatial resolution imaging of action potentials.^5,6 An MEA is an array of sub-cellular-sized electrodes that can measure the extracellular action potential by recording the field potential on the electrodes⁷ with high temporal resolution similar to that of a patch clamp. The MEA can measure cell activities in the case of long-term culturing, because of its noninvasive property. While the number of readout channels in a passive MEA is very small,⁷ a CMOS-MEA expands this number to thousands of channels and provides the 2D imaging, through integration of the readout circuits and microelectrodes on the same CMOS chip. The extracellular signal is very small and low-noise readout channels are needed.⁸ When the intracellular signal, which indicates the transient change of the voltage drop across the cell membrane, is approximately 70 mV peak-to-peak, the extracellular signal, which corresponds to the transient change of ion density outside the cell membrane due to ion channel activity, is of the order of 100 μV peak-to-peak or less. The CMOS-MEA was introduced to increase the number of readout channels which can measure such a small signal with a low noise level.

Various implementation methods have been proposed in previous works on the CMOS-MEA. However, scaling of the readout channel number and the electrode density is problematic, as it increases the noise in the readout channels. This trade-off problem mainly arises because of the shrinking of the transistor dimension on the readout channels, and has not yet been completely overcome.⁹ In this paper, we define a “highly scalable” CMOS-MEA as an array in which such a large number of readout channels and a high electrode density are feasibly achieved, in conjunction with sufficiently low noise level to measure a neuron action potential by overcoming the trade-off problem.

Thus, the present work aims to overcome the trade-off problem and presents a 24‐μm-pitch prototype CMOS-MEA chip with 6912 readout channels at 12 kHz and 23.2‐μV_rms random noise. The CMOS-MEA chip is fabricated by extending a Si CMOS process to fabricate a platinum electrode for a sensing electrode. Although the prototype CMOS-MEA has advantages in terms of the large readout channel number and high electrode density, similar to a previous work with simplex in-pixel circuit and a large number of readout channels,¹⁰ the noise in the readout channel is also reduced to less than half that reported in the previous work, by utilizing low noise and high-gain amplifier design. Further, the action potential is clearly observed for cardiomyocytes using the CMOS-MEA proposed in this work.

The previously proposed CMOS-MEA implementation methods have been classified into two types, i.e., those using a switching matrix (SM) and those based on active pixel sensors (APS).⁹ 

Figure 1(a) shows the example of SM implementation.^11,12 It has the advantages of greater electrode density and small readout noise, but the disadvantage of a lower number of readout channels compared to the alternative. In this design, each pixel is composed of a switching transistor and a local memory only, to connect selected pixels to peripheral readout circuits such as high-gain amplifiers, band pass filters and analog-to-digital converters (ADCs). The small number of circuit elements in each pixel contributes to a small pixel area, and thus, high electrode density. The high-gain amplifier can reduce input-referred noise induced by the ADCs by amplifying the signal amplitude before input to the ADCs, and the band pass filter suppresses the integral noise density by limiting the frequency (f) band to values within the AP signal (AP Band). However, a larger area is required to implement the high-gain amplifier and the band pass filter, and thus, the number of readout channels is limited. This is because a large number of circuit elements (such as multiple transistors or capacitors) are needed,¹¹ and a large amplifier transistor dimension is needed to reduce the noise induced in the transistor itself.

In contrast, the APS implementation facilitates an increased number of readout channels through integration of part of the readout circuits in each pixel and dynamically switching of the connection from the pixels to the peripheral readout circuits by scanning signals from a row decoder. Figure 1(b) shows an example of an APS implementation in which a high-gain amplifier and band pass filters are integrated in each pixel.^13,14 The area of the readout circuits in the peripheral area is considerably smaller than that of the SM implementation, because of the integration of the amplifier and the filters in each pixel. The number of readout channels can be increased because of the smaller area of the peripheral readout circuits. Furthermore, dynamic switching and multiplexing of the readout pixels increases the total number of readout channels above the number of peripheral readout channels. However, the pixel size increases because of the integration of such complex circuits in each pixel. The pixel size could be reduced by reducing the transistor size or removing some of the circuit elements; however, the noise would then be increased.¹⁵ 

The in-pixel circuits must be simplified dramatically to circuits comprised of a buffer amplifier and switching transistor only, as shown in Fig. 1(c), ^5,10 so as to reduce the pixel pitch in the same manner as SM implementation. Although this approach may be the best candidate for scalability of the readout channel number and the electrode density, the noise should be increased,¹⁰ because of the lack of noise-reduction circuits in the readout channel.

These three types of examples show the trade-off problem between the readout channel number, the electrode density, and the readout noise. In this work, we aim to overcome the noise trade-off in the APS readout implementation using a simplex in-pixel circuit which exploits the scalability of readout channel number and electrode density, so as to obtain a highly scalable CMOS-MEA.

Figures 2(a) and 2(b) schematically show the readout channel implementation for the CMOS-MEA employed in this work. Six thousand nine hundred and twelve channels, which are selected from entire 27 648 pixels in the array, can be read out at a 12-kfps (frames per a second) rate, by utilizing an APS implementation with a simplex in-pixel circuit. The noise in the readout channels is reduced by introducing a low-noise and high-gain amplifier, along with a high-speed single slope ADC (SS-ADC).

The readout circuits in each pixel under each sensing electrode are very simple and contain only two transistors, i.e., the potential-sensing amplification and the row-selection switch, as shown in Fig. 2(a). This pixel circuit is similar to the example of given in Fig. 1(c). Readout pixels are selected and connected to the column circuit, by scanning signals from the row decoder to the row-selection switches in each pixel and the field potential on the electrode in the selected pixel can be read. The 216 columns and eight rows in the pixel array can be read simultaneously with the 1728 parallel vertical signal lines (VSLs) and the column circuits at a 48-ksps (samples per a second) sampling speed. Overall, 32 rows, and thus, 6912 pixels of the entire 27 648 pixels array, can be read at a 12-kfps rate as a result of fourfold repetition of the simultaneous parallel readout.

One readout channel is composed of a high-gain amplifier and a SS-ADC, as shown in Fig. 2(b). High-speed and low noise analog to digital conversion is performed by the high-gain amplifier and the SS-ADC. The SS-ADC performs 48-ksps high-speed analog-to-digital conversion with 12-bit resolution, because the SS-ADC has advantages for high-speed data conversion through use of a high-speed input clock.¹⁶ The high-gain amplifier can reduce the noise induced in the SS-ADC in the same manner as that in SM implementation. In addition, an amplification transistor in a selected pixel acts as the first-stage transistor of the high-gain amplifier. This reduces the noise induced in the amplifier itself and the area of the amplifier, because the number of noise sources in the readout channels is reduced compared with the previous implementation, such as the proposed two-stage amplifier with an in-pixel buffer amplifier and a column high-gain amplifier.³ 

This increased number of electrodes and readout channels can be integrated on a small chip having a length of less than 9 mm, as shown in Fig. 3. This small chip size can be achieved because of the small areas of the pixels and the column circuits.

The prototype chip was fabricated through a 0.14 μm 1-poly 4-metal CMOS process. This involved an optimized frontend process for reducing transistor noise and an extended backend process for fabrication of a platinum electrode for a sensing electrode, following the formation of the top metal layer.

The amplifier in the pixel is very important for noise reduction in the readout channels for the implementation in this work. This amplifier was designed using four-parallel wide-width transistors. Note that the width of the amplifier transistor in pixel should be as wide as possible, so as to reduce the noise induced in the amplifier transistor itself. However, the transistor dimension must be smaller than the pixel pitch. The four-parallel transistors can increase the equivalent width of the amplifier than the pixel pitch. In this prototype chip, the total active area of the amplifier is less than 41 μm². Here, the active area includes the channel area and source-drain contact area. Because of the simplex in-pixel circuit, the amplifier can occupy almost all the pixel area, and the small active area contributes to the possibility of decreasing the pixel pitch to 10 μm, which is equivalent to 100 μm² pixel area. The pitch of column circuit was only 3.1 μm. This can increase the number of column circuits, and thus, the total number of readout channels. Note that this small pitch can be achieved using a small-area column circuit. In principle, the small area of the in-pixel amplifier and the small pitch of column circuits can reduce the electrode pitch to approximately 10 μm. However, we relaxed the pitch to 24 μm in this prototype implementation, so as to integrate several test structures in each pixel. In addition, the total number of sensing electrodes was 24 192 in the prototype, because of the dummy pixels at each of the 12 columns on both sides of the array, along with the four arrays of test pixels with 12 columns and eight rows in the active area. The dummy or test pixels had in-pixel readout circuits, but no sensing electrode.

Figure 4(a) shows a random noise distribution with 370 readout channels in one of the fabricated prototype chips. The noise value was measured with a fixed voltage at the input node of the pixel amplifier, without electrolyte. The standard deviation of the output signal variation was calculated for the random noise value of each readout channel. The median value of the random noise distribution with 370 channels was defined as the chip random noise, being 23.2 μV_rms. The inset of Fig. 4 shows the f spectrum of the noise on a single readout channel. The 1/f noise and power supply noise at lower f and the thermal noise at higher f were integrated in the noise value. The chip random noise was reduced to 15.3 μV_rms by limiting the f band to AP band from 300 Hz to 3.3 kHz, with digital finite impulse response (FIR) filter postprocessing, as shown in Fig. 4(b). The inset of Fig. 4(b) shows the reduction of the noise power in the lower- and higher-frequency region.

The postprocess filtering can reduce the noise as shown earlier, but cannot reduce the noise in the AP band and the folded high f noise through ADC sampling. We must reduce these noise sources to reduce the noise further.

Table I shows a comparison of the performance of the CMOS-MEA developed in this work with similar devices reported in previous works. As mentioned in Sec. II, the channel number or the electrode density are limited for SM implementation^12,15 or APS implementation with a complex in-pixel circuit,^13–15 respectively. The complexity of the in-pixel circuit is indicated by the number of analog transistors (Tr.) in each pixel. From the table, it can be determined that the random noise was larger than 40 μV_rms in previous works involving APS with simplex in-pixel circuits; however, the channel number is larger than the SM implementation and the pixel pitch is smaller. Thus, the electrode density is higher.¹⁰ In this work, although the simplicity of in-pixel circuit and the larger number of readout channels is the same as in Ref. 10, the noise was reduced to less than half the values reported in Ref. 10, and further, was comparable to those reported in previous works involving APS with a complex in-pixel circuit.^14,15 This lower noise level could be achieved by optimizing the design of the sensing-amplification transistor and by improving the circuit configuration, as mentioned in Sec. III.

This shows the possibility to reduce the noise with the CMOS-MEA developed in this work, as it can be regarded as a highly scalable MEA. While the readout channel numbers and electrode density in the prototype chip were still lower than those in the other works, these are scalable because of the small dimension and simple in-pixel circuit, and the small pitch of the column circuit, as mentioned in Sec. III.

To compare the MEA scaling, we defined the FoM, where

Here, N_c is the number of channels (ch), F_r is the frame rate (kfps), D_e is the electrode density (μm⁻²), and RN is the random noise (μV_rms). The FoM indicates the number of channels that can be integrated in the same area, with the same readout speed and the same random noise.

In this study, the FoM was evaluated to be 6.21 [kch/(sec μm² μV_rms)] with the noise value for full bandwidth. This result is close to the top-tier result of approximately 10 [kch/(sec  μm² μV_rm)] recorded in previous works, as shown in Table I.

Figure 5(a) shows a micrograph of rat cardiomyocytes [Cardiomyocyte Culture Kit T-2 (Rat), Cosmo Bio Co., Ltd., Tokyo, Japan] cultured for approximately 7 days in 37 °C on the prototype MEA following coating of the sensing electrode and chip surface with collagen. Figure 5(b) shows the measured action potentials recorded with one of the electrodes on the prototype chip. Here, the spontaneous action potential signal was clearly observed with a high signal to noise ratio, because of the low noise of the prototype chip. However, this prototype chip was not suitable for analysis of the cardiomyocyte network activity, because of the considerably smaller dynamic range compared with the variation of the potential offset on the electrodes. Figure 6 shows the distribution of the potential offset on 6048 electrodes with electrolyte. The offset range of the electrode potential was more than 20 mV, and only 50% of the electrodes was covered by the readout dynamic range (approximately 4 mV). Hence, we analyzed the cardiomyocyte network activity using a different prototype chip, which could measure a wider range of signal amplitudes (up to 65 mV). The random noise was higher in the wider-range prototype because the amplitude at the high-gain amplifier in the column circuit was decreased to broaden the dynamic range; however, we could still observe the action potential from cardiomyocyte, because of the sufficiently high action potential signal level.

Figure 7 shows the spontaneous action potential distribution and propagation on 6912 readout pixels (6048 sensing electrodes) along a cell network. The time and spatial distribution were finely resolved because of the larger number of channels and the sufficiently high electrode density. Further, the signal amplitude distribution and the propagation speed could be determined from the measurement results, as shown in Figs. 8(a) and 8(b). The signal amplitude was defined as the peak-to-peak difference on each electrode within a 42.7-ms (512 frames) measurement. The amplitude distribution may indicate the existence and activity of the cells on the electrodes, as shown in Fig. 8(a). Further, the time stamps of the negative peaks on each electrode are plotted in Fig. 8(b). By considering the time stamp and the electrode distance, the propagation speed could be calculated as being approximately 20 cm/s, as shown in Fig. 9. This value is reasonable for rat cardiomyocytes.¹⁷ 

Our current research focus is the measurement of action potentials on neuron cells. For that purpose, in the CMOS-MEA reported herein, the dynamic range should be expanded to cover the entire range of potential-offsets on each electrode, and the noise should be further reduced. In the most recent experiments, the dynamic range was expanded to 13 mV with retention of the same noise level. The extended dynamic range can cover the potential offset of the 96% electrodes with the distribution shown in Fig. 6. In addition, the noise can be decreased to 7.47 μV_rms at full band width with the reduction of the channel number to 432 channels. The channel number was reduced because the size of the column circuit was increased in order to reduce the noise and because the prototype chip size was limited. However, the pitch of the column circuit remained at 12.4 μm. The number of circuit columns and readout channels can be increased with only a slight increase in the chip size. We have started to observe action potentials on neuron cells using the improved prototype CMOS-MEA chips. In future, we will realize a CMOS-MEA design with a larger number of channels and higher electrode density by applying this highly scalable technology with the small-pitch column circuit and the small-dimension in-pixel amplifier.

The CMOS-MEA is now the best candidate for high-resolution imaging of action potentials on cultured cells. Here, we aimed to reduce the random noise in a CMOS-MEA readout circuit for the case of APS implementation with simplex in-pixel circuit, so as to overcome the trade-off between the number of channels, the electrode density, and the random noise. Hence, the noise was successfully reduced to 23.2 μV_rms using the fabricated proto-type CMOS-MEA chip with 24 μm-pitch and 6912 readout channels array; this result indicates the advantage provided by the CMOS-MEA developed in this work, which exhibits high scalability. In addition, the action potentials on cardiomyocytes were clearly observed using the prototype chip, because of the successful noise reduction. The time and spatial distributions were finely resolved following analysis of the measurement results; this was facilitated by the relatively high electrode density and large number of channels. Recently, we began to measure the action potentials on neuron cells using the chip which was improved by expanding the dynamic range and further reducing the noise. In the near future, we aim to realize a higher-scale CMOS-MEA by applying this highly scalable technology.

The authors would like to thank Editage (www.editage.jp) for English language editing.